What Is RISC-V? An Open Alternative to x86 and Arm Explained

RISC-V is an open Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing (RISC) principles, which favour a small, simple and regular instruction set. Anyone can implement it without paying an ISA licence fee, and it is modular and extensible, so designers can pick only the extensions they need and add their own custom instructions. That is the main difference from x86, which is controlled by Intel and AMD, and from Arm, which is licensed by Arm Holdings for a fee and royalty.

Key takeaways

• RISC-V is a specification, not a chip. Cores built to it can be open source or proprietary.
• The ISA is licence-free and maintained by RISC-V International, a non-profit based in Switzerland. It began at UC Berkeley in 2010.
• A small base integer ISA (RV32I, RV64I) is combined with standard extensions such as M, A, F, D, C and V.
• It is already widely shipped in embedded controllers and is moving into application processors, automotive and data-centre accelerators.
• Its biggest gap against x86 and Arm is the maturity of the software ecosystem for high-end computing, which is closing but not closed.

Key features of RISC-V

• Load-store architecture: only load and store instructions access memory; arithmetic works on registers. This simplifies memory access and instruction execution.
• Simple, regular 32-bit instruction format: the base instructions are 32 bits long with register fields in fixed positions, which makes decoding efficient. Correction to the original: the format is not strictly fixed-length, because the standard C (compressed) extension adds 16-bit instructions and the encoding allows longer ones.
• A modest, clean register file: 32 general-purpose integer registers (x0 is hard-wired to zero), or 16 in the embedded RV32E/RV64E variants. Correction to the original: 32 registers is not a small number compared with x86-64's 16; the point is that the register model is simple, with no special-purpose flags register.
• Base integer ISAs and extensions: RV32I (32-bit) and RV64I (64-bit) are the base integer instruction sets, with RV128I defined but rarely used. Correction: these are base ISAs rather than extensions. Standard extensions add multiply and divide (M), atomics (A), floating point (F, D), compressed instructions (C) and vectors (V).
• Room for custom instructions: opcode space is reserved for vendor extensions, so a team can add, for example, a few cryptographic or DSP instructions without breaking compatibility with standard software.

How RISC-V compares with x86 and Arm

Aspect	x86	Arm	RISC-V
Style	CISC, variable length (1 to 15 bytes)	RISC, mostly 32-bit (plus Thumb 16/32-bit)	RISC, 32-bit base plus optional 16-bit compressed
Who controls it	Intel and AMD	Arm Holdings	RISC-V International, open membership
Licensing	Not licensed to new entrants	Licence fee plus royalty	No ISA fee; cores may be free or commercially licensed
Custom instructions	No	Limited, in selected cores	Yes, reserved opcode space
Software maturity	Very high (PC, server)	Very high (mobile, growing in server)	Strong in embedded, growing in Linux and Android

Where RISC-V is used

RISC-V is suitable for custom silicon chips, as a soft core in an FPGA, or as a high-performance software virtual machine. It has been used in a wide range of applications, including embedded systems, automotive systems, disk drives, artificial intelligence and machine learning. Companies like Apple, Samsung and Qualcomm rely on Arm processors for their main application cores, while RISC-V is gaining traction in various industries, including aerospace, automotive and high-performance computing. Many SoCs that use Arm or x86 application cores already contain RISC-V microcontrollers inside for power management, security or I/O control.

A small example

Adding two numbers from memory shows the load-store style. In RISC-V assembly:

lw   t0, 0(a0)     # load word at address in a0
lw   t1, 4(a0)     # load next word
add  t2, t0, t1    # add registers
sw   t2, 8(a0)     # store the result

An x86 processor could add a memory operand directly to a register in one instruction. RISC-V keeps memory access and arithmetic separate, which keeps each instruction simple to decode and pipeline.

Maturity and outlook

When this post first appeared in December 2023, the view was that, in comparison to x86 and Arm, RISC-V was still in development and not yet commercially ready for widespread adoption in mainstream PCs, phones and servers. That remains broadly true for those markets, while in microcontrollers and embedded cores RISC-V is already shipping in very large volumes. Since then, RISC-V International ratified the RVA23 application profile (October 2024), which gives operating system and application developers a common baseline to target, an important step towards general-purpose software compatibility.

It offers clear advantages, such as the ability to add custom extensions and customise the chip for various applications. The future of RISC-V remains uncertain in the high-end segments, as it faces competition from established architectures like x86 and Arm, but it has the potential to challenge them in specific application areas.

Video: RISC-V explained

This video explains what RISC-V is all about, including its origins, key market players, hardware, applications, intellectual property (IP), and the likely role of global politics and international trade barriers in determining RISC-V's success.

FAQ

Is RISC-V free to use?

The ISA specification is free to implement. A particular core design may still be a commercial product with its own licence.

Can RISC-V run Linux?

Yes. RV64 cores with the standard extensions and a memory management unit run mainline Linux, and several distributions provide RISC-V builds.

Is RISC-V faster than Arm?

Speed depends on the microarchitecture, process node and design effort, not the ISA alone. A well-designed core on either ISA can be competitive.

Why does geopolitics matter for RISC-V?

Because no single company controls the ISA, many countries see it as a way to reduce dependence on licensed architectures, which has encouraged investment and also drawn regulatory attention.