Displaying posts in the categoryRISC-V
RISC-V articles
Special Reports
Special report, February 2026, reviewed and corrected in November 2026. Market figures are as published by the sources named; most are forecasts and have not been re-verified. Edge AI means running AI models on the device where the data is created, such as a phone, a car, a robot, a camera or a sensor, instead of sending everything to a cloud data centre. In 2025 and 2026 it moved from pilots to real deployment, driven by three things together…
by
Murugavel Ganesan
February 02, 2026
Semiconductor Business
Tech Trendspotter , June 2025 New players can win in automotive microcontrollers with RISC-V by picking a narrow, fast-growing niche, building on licensable cores and safety-ready IP rather than designing everything from scratch, and closing the software and functional safety gaps that make car makers cautious. RISC-V removes the architecture licence fee and the dependence on a single CPU vendor, but it does not remove the cost of ISO 26262 ce…
by
Murugavel Ganesan
June 19, 2025
Video
RISC-V is an open Instruction Set Architecture (ISA) based on Reduced Instruction Set Computing (RISC) principles, which favour a small, simple and regular instruction set. Anyone can implement it without paying an ISA licence fee, and it is modular and extensible, so designers can pick only the extensions they need and add their own custom instructions. That is the main difference from x86, which is controlled by Intel and AMD, and from Arm, wh…
by
Murugavel Ganesan
December 24, 2023
