The Story of the Chiplet
Act I: The Monolith and Its Limits
For fifty years, the semiconductor industry worshipped at the altar of the monolith.
One die. One process. One yield equation. Moore's Law was the gospel, and shrinking transistors was the sermon preached every two years. Intel, IBM, and later TSMC kept the faith. The monolithic SoC was the pinnacle — everything integrated, everything optimized, nothing wasted on the interface between chips.
It worked beautifully. Until it didn't.
By the time process nodes reached 7nm, then 5nm, the economics started to crack. A 800mm² monolithic die wasn't just expensive — it was brutally wasteful. A single defect anywhere on that enormous canvas killed the whole chip. Yields fell. Costs exploded. The leading edge became the bleeding edge.
And then there was the deeper problem: not every function needed to be on the bleeding edge. Your SerDes PHY doesn't need 3nm. Your embedded SRAM is most efficient at mature nodes. Your analog blocks hate the leakage currents of advanced nodes. The monolith forced every circuit to pay the same premium — even the ones that didn't deserve it.
Act II: The Idea That Was Always There
Chiplets weren't invented. They were remembered.
Multi-chip modules (MCMs) had existed since the 1980s. IBM's mainframes were built from disaggregated tiles long before anyone called them chiplets. The idea of assembling a system from best-in-class parts rather than forcing everything onto one die was obvious to anyone who thought about it.
What changed wasn't the concept. What changed was the interconnect.
The bottleneck was always the same: once you split a monolith apart, the bandwidth between the pieces collapses, power consumption at the interfaces soars, and latency creeps in. The die-to-die link was the wound that bled out every chiplet proposal before it could prove itself.
That changed in the 2010s — slowly, then suddenly.
TSMC's CoWoS brought HBM stacks onto the same interposer as logic dies. Intel's EMIB (Embedded Multi-die Interconnect Bridge) threaded a silicon bridge through a cheap organic substrate, stitching Foveros tiles together. And then came the standards wars — UCIe, BoW, AIB — everyone trying to own the language that dies would speak to each other.
The interconnect problem wasn't solved. But it was tamed.
Act III: AMD Bets the Company
The chiplet story has a hero, and it is AMD circa 2017.
Under Lisa Su, AMD didn't just adopt chiplets as a technical strategy — they used it as a business strategy to outmaneuver Intel at a fraction of the R&D cost. The Zen architecture was modular by design. The core compute die (CCD) and the I/O die (IOD) were fabricated separately — CCDs on TSMC's leading node for transistor efficiency, the IOD on a mature node for cost.
The result: Ryzen 3000. Threadripper. EPYC Rome.
Suddenly, a company without Intel's fabs and without Intel's budget was shipping products that beat Intel in core count, performance-per-watt, and price-per-thread. Not because AMD had better engineers. Because AMD had a better architecture philosophy.
The chiplet had won its first decisive battle.
Act IV: Everyone Comes to the Table
After AMD's success, the industry didn't gradually warm to chiplets. It stampeded.
Intel reversed course entirely. Ponte Vecchio, their data center GPU, was assembled from 47 active tiles across five different process technologies. It was the most complex chiplet integration ever attempted — and it was a manufacturing nightmare that nearly broke them. But they committed.
Apple quietly became the most sophisticated chiplet integrator in consumer silicon. The M-series chips stacked DRAM and logic in SoIP (System on Integrated Package) configurations that nobody else could touch in power efficiency. They didn't talk about chiplets — they just shipped products that demolished the competition.
NVIDIA remained the holdout, preferring monolithic dies for their GPU compute engines but stacking HBM aggressively for memory bandwidth. Then Blackwell arrived: two reticle-sized dies stitched together by a 10TB/s NVLink-C2C interface, functionally behaving as one. Even NVIDIA had crossed the threshold.
In China, where access to advanced nodes was throttled by export controls, chiplets became a survival strategy. If you can't get 3nm, you assemble 7nm dies cleverly. Geopolitics accelerated the technology.
Act V: The Standard That Doesn't Exist Yet
Here is where the story gets uncomfortable.
Every chiplet ecosystem today is proprietary. AMD's dies don't talk to Intel's dies. NVIDIA's NVLink is a walled garden. Apple's package is a sealed cathedral. The promise of chiplets — that you could mix and match best-in-class silicon from multiple vendors like PCIe cards in a socket — has not arrived.
UCIe (Universal Chiplet Interconnect Express) was supposed to be the answer. Launched in 2022 with 100+ member companies, it defined die-to-die protocols across package and short-reach interconnect. The spec exists. The silicon is beginning to appear.
But here's the tension: the companies that win with chiplets today win because their integration is proprietary. AMD's Infinity Fabric is a competitive moat. Apple's die-to-die bandwidth is a secret weapon. Standardization threatens the very advantage that made chiplets valuable.
The industry wants open standards for chiplets the same way it wants open standards for everything — until the moment those standards would erase a competitive edge. Then the working groups slow down. The silicon samples are delayed. The test vehicles are quietly shelved.
UCIe will happen. The question is whether it arrives as a revolution or as a footnote.
Act VI: What Chiplets Mean for the Next Decade
The chiplet era changes everything downstream of it.
For fabs: TSMC, Samsung, and Intel Foundry are now competing not just on node performance but on packaging. CoWoS, SoIC, Foveros, EMIB — advanced packaging is the new process node. The capital investment in packaging lines now rivals the investment in the fabs themselves.
For design teams: Disaggregating a monolith into chiplets requires new disciplines. Die-to-die interface design. Thermal management across heterogeneous tiles. Yield partitioning analysis. Physical co-design between tiles from different vendors. The EDA tools are still catching up.
For automotive: The chiplet thesis is arriving slowly in cars. Zonal E/E architectures demand high-bandwidth, low-latency die-to-die links inside domain controllers. SerDes PHYs, compute accelerators, and safety monitors are natural candidates for disaggregation. AEC-Q100 qualification for chiplet assemblies doesn't yet exist as a coherent standard — that gap is an opportunity and a risk simultaneously.
For startups: Chiplets democratize differentiation. A startup can license a process-optimized compute die from one foundry, add a proprietary accelerator tile built on a specialty node, and assemble a system that no monolithic SoC could match in cost or performance. The barrier to entry in silicon is falling — not to zero, but meaningfully lower.
For geopolitics: The chiplet is a unit of strategic value. Nations are building chiplet roadmaps the way they once built missile programs. Advanced packaging capability is now as strategically sensitive as the fabs themselves.
Epilogue: The Deeper Truth
The chiplet is not a technology. It is a philosophy.
It says: the whole does not have to come from a single place. The best memory, the best compute, the best I/O, the best analog — let each be built where it is most efficiently made, then assembled into something that none of them could be alone.
It is, at its core, a rejection of the tyranny of the monolith.
And in that, it echoes something much older than semiconductors — the insight that the most resilient and capable systems are modular, that specialization and integration are not opposites but partners, and that the interface between things is where the real engineering lives.
The chiplet era is just beginning. The packaging wars, the standards battles, the automotive qualifications, the geopolitical maneuvering — these are Act One of a very long story.
The die has been cast. Literally.
Your comments will be moderated before it appears here.