A chiplet is a small die designed to be combined with other dies in one package so that together they behave like a single large chip. The idea took off because giant monolithic dies at advanced nodes became too costly to yield, and because not every circuit benefits from the newest process. Better die-to-die interconnect and advanced packaging made it practical, AMD proved it commercially with Zen 2 in 2019, and Intel, Apple and NVIDIA followed. This is the story of how that happened, and of what it means for the next decade.
Key takeaways
- Large monolithic dies lose yield quickly as area grows; splitting them into smaller dies recovers much of that loss.
- Chiplets let each function use the process node that suits it best: logic on the leading edge, I/O, analog and some memory on mature nodes.
- The enabling technology was the die-to-die interconnect and advanced packaging (CoWoS, EMIB, Foveros, hybrid bonding), not the idea itself.
- Commercial chiplet ecosystems are still largely proprietary; UCIe is the main attempt at an open die-to-die standard.
- Packaging is now a competitive and strategic battleground, in fabs, in design teams, in automotive and in geopolitics.
Act I: The monolith and its limits
For fifty years, the semiconductor industry worshipped at the altar of the monolith.
One die. One process. One yield equation. Moore's Law was the gospel, and shrinking transistors was the sermon preached every two years. Intel, IBM, and later TSMC kept the faith. The monolithic SoC was the pinnacle: everything integrated, everything optimised, nothing wasted on the interface between chips.
It worked beautifully. Until it didn't.
By the time process nodes reached 7nm, then 5nm, the economics started to crack. An 800mm² monolithic die wasn't just expensive. It was brutally wasteful. A single defect anywhere on that enormous canvas killed the whole chip. Yields fell. Costs exploded. The leading edge became the bleeding edge.
The yield arithmetic (illustrative numbers)
A simple Poisson yield model gives the fraction of good dies as Y = e-D×A, where D is defect density and A is die area. Take an illustrative D of 0.1 defects per cm²:
| Design | Area per die | Yield per die | Comment |
|---|---|---|---|
| One monolithic die | 800 mm² (8 cm²) | e-0.8 ≈ 45% | More than half the wafer area is scrapped |
| Four chiplets | 200 mm² (2 cm²) | e-0.2 ≈ 82% | Bad dies are discarded before assembly |
Because each chiplet is tested before packaging (the known-good-die step), only good dies are assembled. The silicon cost per working product falls sharply, though some of that saving is spent on the extra die-to-die interface area, packaging and test. Real defect densities and models vary by foundry and node.
And then there was the deeper problem: not every function needed to be on the bleeding edge. Your SerDes PHY doesn't need 3nm. Your embedded SRAM is often most cost-efficient at mature nodes, because SRAM cells have stopped shrinking much at the leading edge. Your analog blocks hate the leakage currents and low supply voltages of advanced nodes. The monolith forced every circuit to pay the same premium, even the ones that didn't deserve it.
Act II: The idea that was always there
Chiplets weren't invented. They were remembered.
Multi-chip modules (MCMs) had existed since the 1980s. IBM's mainframes were built from multi-chip modules long before anyone called them chiplets. The idea of assembling a system from best-in-class parts rather than forcing everything onto one die was obvious to anyone who thought about it.
What changed wasn't the concept. What changed was the interconnect.
The bottleneck was always the same: once you split a monolith apart, the bandwidth between the pieces collapses, power consumption at the interfaces soars, and latency creeps in. The die-to-die link was the wound that bled out every chiplet proposal before it could prove itself.
That changed in the 2010s, slowly and then suddenly.
TSMC's CoWoS put logic dies and, later, HBM stacks side by side on a silicon interposer. Intel's EMIB (Embedded Multi-die Interconnect Bridge) embedded a small silicon bridge in a cheaper organic substrate to join neighbouring dies, and Intel's Foveros stacked dies face to face in 3D; the two were later combined as Co-EMIB. And then came the standards wars (UCIe, BoW, AIB), with everyone trying to own the language that dies would speak to each other.
The interconnect problem wasn't solved. But it was tamed.
Act III: AMD bets the company
The chiplet story has a hero, and it is AMD in the years from 2017.
Under Lisa Su, AMD didn't just adopt chiplets as a technical strategy. It used them as a business strategy to outmanoeuvre Intel at a fraction of the R&D cost. The Zen architecture was modular by design. First-generation EPYC (Naples, 2017) already joined four identical dies in one package. With Zen 2 in 2019, AMD split the design: the core compute die (CCD) and the I/O die (IOD) were fabricated separately, CCDs on TSMC's 7nm node for transistor efficiency, the IOD on a mature GlobalFoundries node for cost.
The result: Ryzen 3000. Third-generation Threadripper. EPYC Rome.
Suddenly, a company without Intel's fabs and without Intel's budget was shipping products that beat Intel in core count, performance-per-watt, and price-per-thread. Not because AMD had better engineers. Because AMD had a better architecture philosophy.
The chiplet had won its first decisive battle.
Act IV: Everyone comes to the table
After AMD's success, the industry didn't gradually warm to chiplets. It stampeded.
Intel reversed course entirely. Ponte Vecchio, its data centre GPU, was assembled from 47 active tiles across five different process technologies, as Intel described it. It was one of the most complex chiplet integrations ever attempted, and it was a manufacturing nightmare that nearly broke them. But they committed.
Apple quietly became the most sophisticated chiplet integrator in consumer silicon. The M-series chips put DRAM in the same package as the processor, and the Ultra parts joined two dies with a silicon bridge Apple calls UltraFusion. The power efficiency was hard for anyone to match. Apple didn't talk about chiplets; it just shipped products that demolished the competition.
NVIDIA remained the holdout, preferring monolithic dies for its GPU compute engines but stacking HBM aggressively for memory bandwidth. Then Blackwell arrived: two reticle-sized dies stitched together by a 10 TB/s die-to-die link, functionally behaving as one GPU. NVIDIA calls that link NV-HBI (the original post named it NVLink-C2C, which is NVIDIA's separate chip-to-chip link between Grace CPUs and GPUs). Even NVIDIA had crossed the threshold.
In China, where access to advanced nodes was throttled by export controls, chiplets became a survival strategy. If you can't get 3nm, you assemble 7nm dies cleverly. Geopolitics accelerated the technology.
Milestones at a glance
| Year | Milestone |
|---|---|
| 1980s | Multi-chip modules in mainframes |
| 2010s | TSMC CoWoS and Intel EMIB reach production; HBM moves onto the package |
| 2017 | AMD EPYC Naples joins four dies in one package |
| 2019 | AMD Zen 2 separates compute (CCD) and I/O (IOD) dies on different nodes |
| 2022 | UCIe consortium formed to define an open die-to-die interconnect; Apple M1 Ultra uses UltraFusion |
| 2022 to 2023 | Intel Ponte Vecchio and Sapphire Rapids ship with multiple tiles |
| 2024 | NVIDIA Blackwell joins two large dies with a 10 TB/s link |
Act V: The standard that doesn't exist yet
Here is where the story gets uncomfortable.
The large commercial chiplet ecosystems today are proprietary. AMD's dies don't talk to Intel's dies. NVIDIA's NVLink is a walled garden. Apple's package is a sealed cathedral. The promise of chiplets, that you could mix and match best-in-class silicon from multiple vendors like PCIe cards in a socket, has not arrived.
UCIe (Universal Chiplet Interconnect Express) was supposed to be the answer. Launched in 2022 by a group of founding companies and grown to well over 100 members since, it defines die-to-die physical layers and protocols for standard and advanced packages. The spec exists. The silicon is beginning to appear.
But here's the tension: the companies that win with chiplets today win because their integration is proprietary. AMD's Infinity Fabric is a competitive moat. Apple's die-to-die bandwidth is a secret weapon. Standardisation threatens the very advantage that made chiplets valuable.
The industry wants open standards for chiplets the same way it wants open standards for everything, until the moment those standards would erase a competitive edge. Then the working groups slow down. The silicon samples are delayed. The test vehicles are quietly shelved.
UCIe will happen. The question is whether it arrives as a revolution or as a footnote.
Act VI: What chiplets mean for the next decade
The chiplet era changes everything downstream of it.
For fabs: TSMC, Samsung, and Intel Foundry are now competing not just on node performance but on packaging. CoWoS, SoIC, Foveros, EMIB: advanced packaging is the new process node. The capital investment in packaging lines now rivals, in the author's view, the investment in the fabs themselves.
For design teams: disaggregating a monolith into chiplets requires new disciplines. Die-to-die interface design. Thermal management across heterogeneous tiles. Yield partitioning analysis. Physical co-design between tiles from different vendors. The EDA tools are still catching up.
For automotive: the chiplet thesis is arriving slowly in cars. Zonal E/E architectures demand high-bandwidth, low-latency die-to-die links inside domain controllers. SerDes PHYs, compute accelerators, and safety monitors are natural candidates for disaggregation. AEC-Q100 qualification for chiplet assemblies doesn't yet exist as a coherent standard. That gap is an opportunity and a risk simultaneously.
For startups: chiplets democratise differentiation. A startup can license a process-optimised compute die from one supplier, add a proprietary accelerator tile built on a specialty node, and assemble a system that no monolithic SoC could match in cost or performance. The barrier to entry in silicon is falling, not to zero, but meaningfully lower.
For geopolitics: the chiplet is a unit of strategic value. Nations are building chiplet roadmaps the way they once built missile programmes. Advanced packaging capability is now as strategically sensitive as the fabs themselves.
Common misconceptions
- "Chiplets are always cheaper." Not for small dies. Below a certain area, the extra interface logic, packaging and test cost more than the yield gain.
- "A chiplet is just a smaller chip." A chiplet is designed to be useless on its own; it depends on its neighbours through a die-to-die link.
- "Open standards mean plug-and-play today." Electrical compatibility is only part of it. Thermal, mechanical, test and security agreements between vendors are still maturing.
Epilogue: The deeper truth
The chiplet is not a technology. It is a philosophy.
It says: the whole does not have to come from a single place. The best memory, the best compute, the best I/O, the best analog: let each be built where it is most efficiently made, then assembled into something that none of them could be alone.
It is, at its core, a rejection of the tyranny of the monolith.
And in that, it echoes something much older than semiconductors: the insight that the most resilient and capable systems are modular, that specialisation and integration are not opposites but partners, and that the interface between things is where the real engineering lives.
The chiplet era is just beginning. The packaging wars, the standards battles, the automotive qualifications, the geopolitical manoeuvring: these are Act One of a very long story.
The die has been cast. Literally.
FAQ
What is the difference between a chiplet and a multi-chip module?
Both put several dies in one package. A chiplet design splits what would have been one chip into dies built to work together over a dense, low-power die-to-die link, so the result behaves like a single chip.
What is UCIe?
Universal Chiplet Interconnect Express, an open specification for die-to-die links, covering the physical layer and protocol mapping (including PCIe and CXL) for standard and advanced packages.
Why not put everything on the latest node?
Analog circuits, I/O and some SRAM gain little from the newest nodes but pay their full wafer cost, so placing them on mature nodes saves money with little loss in performance.
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