Showing posts with label DDR. Show all posts
Showing posts with label DDR. Show all posts

Understanding system-level energy-management techniques and test

Gina Bonini is the worldwide embedded-system technical-marketing manager for Tektronix. In this article she talks about Power dissipation, Bus energy dissipation, PCI-e low power mode, some power saving modes and low power DDR DRAM.

Dealing with clock jitter in DDR2/DDR3 based designs

For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent pll model integration the whole scenario changed and i was in the middle of a clock jitter related timing check failure. This led me to do some Google search when i found this interesting 3 part article based on the same title.

Defining clock jitter
DDR2/DDR3 functionality
Clock jitter and statistics