Displaying posts in the categoryFormal Verification
Formal Verification articles
Verification
The 2024 Wilson Research Group study put first-silicon success at 14% of projects, the lowest level in two decades, so the appeal of agents in verification is easy to see. The published evidence is more mixed than the demos. In one preprint, the same agent flow and model lifted formal coverage by about 22 points on one design and about 8 on another. In another, assertions that compile and prove caught few injected bugs in a typical run. So the…
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Murugavel Ganesan
November 15, 2026
Verification
IP and full chip verification interviews check whether you can prove a design correct before it becomes silicon. Expect questions on planning, SystemVerilog and UVM testbenches, constrained-random stimulus, coverage, assertions and formal, and on the system-level problems that only appear when every block is connected. The 50 questions below cover all of these, and each now has a short model answer. Verification is the backbone of chip desig…
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Murugavel Ganesan
January 03, 2025
Verification
Equivalence checking proves that two versions of the same design behave identically, for example RTL against the gate-level netlist produced by synthesis. Property checking proves that one design satisfies a set of properties written from the specification, such as "two grants are never active together". Both are formal methods that cover all input values without test vectors, but equivalence checking needs a trusted reference design, …
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Murugavel Ganesan
August 26, 2023
Verification
Formal verification is the use of mathematical analysis, rather than test vectors, to prove that a chip design meets its specification. A formal tool takes the RTL and a set of properties (assertions about how the design must behave) and either proves each property holds for every possible input sequence and reachable state, or returns a counterexample trace that shows exactly how it fails. In semiconductor engineering it is used to find corne…
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Murugavel Ganesan
August 26, 2023
Synthesis
With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It's also production-proven with more physical design closure tools, advanced synthesis tools, ASIC libraries, and IP cores than any other formal verification tool. Many EDA tool vendors rely on Conformal ASIC as an independent standard within their regression suites to verify the results that their own tools produce. Key Feat…
Verification
How many times in the course of a project have you heard of the term Formal Verification? This relatively short on article theorem proving article assumes that you know the basic definition of Formal Verification while we try to see what Theorem proving is in relation to Formal Verification. The theorem proving techniques relate specification and implementation as a theorem in logic to be proven in the context of a proof calculus. The implemen…
Verification
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cannot be ignored or hind-sighted and they are part of the chip design process itself. You may also have known or learnt that there is always a productivity gap, the significance of verification, the very famous pentium bug, the moore's law, that verification cannot be done by simulation itself, the benefits of formal verificati…
Verification
Design verification, must show that the design, expressed at the RTL or structural level, implements the operations described in the data sheet or whatever other specification exists. Verification at the RTL level can be accomplished by means of simulation, but there is a growing tendency to supplement simulation with formal methods such as model checking. At the structural level the use of equivalence checking is becoming standard procedure. In…
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The Editor's Desk
December 16, 2008
Verification
Verification: In order to verify the functional correctness of a design, one needs to capture the model of the behavior of the design in a formal language or use the design itself. In most commercial software development organizations, there is often no formal specification of the program under development. Formal verification is used routinely by only small pockets of the industrial software community, particularly in the areas of protocol veri…
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The Editor's Desk
February 23, 2005
Verification
DFT: manufacturing defects like stuck at "0" or "1". test for set of rules followed during the initial design stage. Formal verification: Verification of the operation of the design, i.e, to see if the design follows spec. gate netlist == RTL (Equivalence checking) using mathematics and statistical analysis to check for eqivalence.
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The Editor's Desk
February 21, 2005
