Displaying posts in the categoryFormal Verification
Technology
Equivalence checking and property checking are two important techniques for verifying the correctness of hardware designs. In this blog post, we will explain the difference between them. Equivalence checking is a portion of a larger discipline called formal verification. This technology uses mathematical modeling techniques to prove that two representations of design exhibit the same behavior. This approach should not be confused with functio…
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Murugavel Ganesan
August 26, 2023
Technology
What is formal verification? Formal verification is an essential part of semiconductor development, but it also requires careful planning, rigorous reviews, and comprehensive metrics to achieve a quantifiable measure of functional verification completeness. By following the steps of formal signoff talked in this article, semiconductor developers can ensure that their designs are correct and quality, and that they are ready for fabrication. Forma…
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Murugavel Ganesan
August 26, 2023
Theorem proving
How many times in the course of a project have you heard of the term Formal Verification? This relatively short on article theorem proving article assumes that you know the basic definition of Formal Verification while we try to see what Theorem proving is in relation to Formal Verification. The theorem proving techniques relate specification and implementation as a theorem in logic to be proven in the context of a proof calculus. The implemen…
Verification
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cannot be ignored or hind-sighted and they are part of the chip design process itself. You may also have known or learnt that there is always a productivity gap, the significance of verification, the very famous pentium bug, the moore's law, that verification cannot be done by simulation itself, the benefits of formal verificati…
Netlist
Design verification, must show that the design, expressed at the RTL or structural level, implements the operations described in the data sheet or whatever other specification exists. Verification at the RTL level can be accomplished by means of simulation, but there is a growing tendency to supplement simulation with formal methods such as model checking. At the structural level the use of equivalence checking is becoming standard procedure. In…
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The Editor's Desk
December 16, 2008
Formal Verification
DFT: manufacturing defects like stuck at "0" or "1". test for set of rules followed during the initial design stage. Formal verification: Verification of the operation of the design, i.e, to see if the design follows spec. gate netlist == RTL (Equivalence checking) using mathematics and statistical analysis to check for eqivalence.
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The Editor's Desk
February 21, 2005
