Showing posts with label Manufacturing. Show all posts
Showing posts with label Manufacturing. Show all posts

China Injects $2.2 Billion Into Local Chip Firm

China's state-backed funds pumped $2.25 billion into a Semiconductor Manufacturing International Corp. wafer plant to support advanced-chip making as Washington tightens technology restrictions on the Asian nation. From a report:

The Semiconductor Manufacturing International Corp. plant's registered capital jumps from $3.5 billion to $6.5 billion after the investment, the company said in an announcement on Friday. The chipmaker's stake in the Shanghai facility will drop from 50.1% to 38.5%, it said. The plant has capacity to produce 6,000 14-nanometer wafers a month and plans to boost that to 35,000. The new investment came as Washington moved to prevent sales to Huawei by chipmakers using U.S. technology. The Commerce Department on Friday said it would require licenses before allowing U.S. technology to be used by the Chinese company or its 114 subsidiaries, including its chip-design unit HiSilicon

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Why High-k dielectrics in sub 45nm nodes?

To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. So, what is it that makes High-K dielectrics so attractive in today's technology scaling raodmaps :-)?

In cutting edge silicon nanoelectronics both high-k and low-k dielectrics are needed to implement fully functional and very high-density integrated circuits, although for drastically different reasons. High-k dielectrics are needed in MOS gate stacks to maintain sufficiently high capacitance of the metal (gate)-dielectric-Si structure in MOS/CMOS transistors. Due to the continued scaling of the channel lengths, and hence reduced gate area, the need to maintain sufficient capacitance of the MOS gate stack was met by gradual decrease of the thickness of SiO2 gate oxide Obviously such scaling cannot continue indefinitely as at a certain point gate oxide will become so thin (thinner than about 1 nm) that, due to excessive tunneling current, it would stop playing the role of an insulator. Hence, dielectric featuring k higher than 3.9, i.e. one assuring same capacitive coupling but at the larger physical thickness of the film, must be used instead of SiO2 as a gate dielectric in advanced MOS/CMOS integrated circuits.

On the opposite end of the spectrum finds itself a multi-layer metallization scheme in which inter-layerdielectric (ILD) is used to electrically insulate metal lines. In this case it is of critical importance that the capacitive coupling between adjacent interconnect lines is as limited as possible. Hence, a low-k dielectric must be used to assure as little capacitive coupling (low “cross-talk”) between interconnect lines as possible.

Whether the problem is with high-k dielectrics for MOS gates or low-k dielectrics for ILDs, lack of viable technical solutions in either of these areas will bring any future progress in mainstream silicon technology to a screeching halt. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO2 and HfSiO2 are widely used by Intel for its 32nm technology nodes for its upcoming processors.