Setup

negative setup and hold time

A negative setup and hold condition is a very interesting proposition in static timing analysis. Support for this type of conditions was added in the Verilog LRM, only in the late 90's (using the $SETUP and $HOLD constructs). The basic idea is something like this: Consider a module with an ideal flop in it. Now, there exists a data path (from primary inputs of module to D of flop) and a clock path (from primary inputs to CLK of flop). Suppos…

Negative hold time

What is a Negative hold time?

Negative hold time is generally seen where a delay is already added in the data path inside the flop. This is usually done by the library vendor. Assume the flop which foundry gives us as a library part that has ports named as CLK-port, Data-port. Now, in essence this is wrapper and should be treated as one. Inside this we have the actual flop whose ports are CLK-in, data-in. CLK-port is connected directly to CLK-in, Data-port goes through some …