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Showing posts with label Performance. Show all posts
Showing posts with label Performance. Show all posts
Home » Posts filed under Performance
Study gives 4G data performance high marks
Handsets operating on 4G cellular networks offer significant improvement in data transfer performance compared to their 3G predecessors, according to a study evaluating the performance of smartphones available from U.S. national carriers conducted by consulting firm Metrico Wireless Inc. More Here.
System Architect for micro-architecture performance analysis and optimization during functional simulation
System Architect is comprised of a set of powerful, on-demand SystemC-compliant functions and analysis tools that enable micro-architecture performance analysis and optimization during functional simulation. The analysis provides a wide range of valuable information showing how to improve performance and power utilization. Seamlessly linked with Summit's Vista IDE , System Architect enables effective and rapid analysis of system performance and architectural tradeoffs using C and SystemC.
The System Architect API function set can be instrumented into any functional code to track tokens of data, log states and attributes. Textual reports and visualization tools allow designers to analyze actual key performance metrics, such as bus contention, memory utilization, and SW instruction distribution - all during standard functional simulation. These metrics are critical for analyzing micro-architecture bottlenecks, bandwidth limitations, and power tradeoffs.
Key Features:
* On-demand SystemC-compliant API functions
* Advanced textual and graphical reports
* Analysis of data throughput and communication latencies
* Dynamic resource utilization analysis (such as memories and FIFO's)
* Software task distribution and processor utilization reports
* Hardware/Software tradeoff analysis
The System Architect API function set can be instrumented into any functional code to track tokens of data, log states and attributes. Textual reports and visualization tools allow designers to analyze actual key performance metrics, such as bus contention, memory utilization, and SW instruction distribution - all during standard functional simulation. These metrics are critical for analyzing micro-architecture bottlenecks, bandwidth limitations, and power tradeoffs.
Key Features:
* On-demand SystemC-compliant API functions
* Advanced textual and graphical reports
* Analysis of data throughput and communication latencies
* Dynamic resource utilization analysis (such as memories and FIFO's)
* Software task distribution and processor utilization reports
* Hardware/Software tradeoff analysis
TI reveals details of 45-nm process
Rumors had been rampant for the past 3 months or so that TI had stopped development on the 45 nm node and moved on to 40nm attributing to lower power advantages and poor performance scaling till this article was published at EETimes.
"The first 45-nanometer chip to be designed by Texas Instruments, and fabricated by a foundry, uses new processing technology never before revealed by TI. The design details of the 45-nanometer process used to lower power by 63 percent and increase performance by 55 percent, compared with its 65-nanometer process, will be revealed Tuesday (Feb. 5) by TI at the International Solid-State Circuits Conference here."
Read on.. (Broken link, corrected now)
"The first 45-nanometer chip to be designed by Texas Instruments, and fabricated by a foundry, uses new processing technology never before revealed by TI. The design details of the 45-nanometer process used to lower power by 63 percent and increase performance by 55 percent, compared with its 65-nanometer process, will be revealed Tuesday (Feb. 5) by TI at the International Solid-State Circuits Conference here."
Read on.. (Broken link, corrected now)