Showing posts with label Power Gating. Show all posts
Showing posts with label Power Gating. Show all posts

Dynamic power supply

Power gating adds enabling signals to a power supply network; dynamic power supply management adjusts supply voltage according to data path criticality. You are asked to take a testcase and upgrade its power supply network to dynamic power supply. How can you verify the power reduction of your technique?

Hierarchy and Power Gating

A scalable approach to chip architecture is essential and valuable since a SOC design today often becomes a component in an even larger chip in subsequent product generations.

To support this portability, module boundaries must be enforced at the power domains level. That is, a given module should belong to a single power domain, not split across several domains. Some tools and flows support RTL process by RTL process assignment to power domains, but this leads to much more complicated implementation and analysis. Clean visibility of the boundaries of a power gated block is key to having a clean, top-down implementation and verification flow.

Although one can in theory nest power gated modules arbitrarily within power gated subsystems which are in turn nested on a shared switched power rail, there are considered benefits in not creating multiple levels of power switching fabric. Power gating is intrusive and ass in some voltage drop and degradation of performance. Cascading multiple voltage drops can lead to unacceptable increases in delay. Even if the design is representeted as hierarchical at the architectural level, the implementation is improved if this is mapped on to a single level of power gating at implementation.

  • Map power gated regions to explicit module boundaries.
  • When partitioning a hierarchical power gating design ensure that the power gating control terms can be mapped back to a flat switching fabric.
  • Avoid control signals passing through power gated or power down regions to other power regions that not hierarchically switched with the first region.
  • Avoid excessively fine power gating granularity unless absolutely required for aggressive leakage power management. Every interface adds implementation and verification challenges and complicates the system level production test challenges.
  • Avoid a power gating system of more that one or two levels.

Retention mechanisms in power gated designs

How can we retain state of some of the registers in the design? How to deal with memory state?

Let me try to explain each one of them based on my recent design experience.
For regular logic blocks, there are multiple ways to wake-up faster without losing much of information.

  • Use retention flops to save state of some important registers. For example state of control block, which forms the heart of the whole system.
  • If the chip is aimed for At-Speed testing, scan chains of the design can be used to scan out the data to an external memory and scan in after wake-up. This may not be as fast as using retention flops.
  • ….. there are many more possible methods.

Again w.r.t to retention flops there were questions about, How many type of retention flops are available.
I have seen 3 types.

  1. Single save/restore pin retention latch (Slave latch being always on)
  2. Single pin balloon Latch
  3. Dual Pin balloon Latch
Pro's and Con's of Single Pin Vs Dual Pin retention flops:

Advantages of Single Pin:

  • Minimal area impact
  • Single signal controls retention

Disadvantages of Single Pin:

  • Performance Impact on the register
  • Hold Time requirements for the input data

Advantage of Dual Pin:

  • Minimal leakage power
  • Minimal performance impact compared to the Single Pin design
  • Minimal dependency on the clock for the control signals.

Disadvantages of Dual Pin:

  • Area Impact
  • More Complex System Design
  • More Buffer Network and AON network required.