Let me try to explain each one of them based on my recent design experience.
For regular logic blocks, there are multiple ways to wake-up faster without losing much of information.
- Use retention flops to save state of some important registers. For example state of control block, which forms the heart of the whole system.
- If the chip is aimed for At-Speed testing, scan chains of the design can be used to scan out the data to an external memory and scan in after wake-up. This may not be as fast as using retention flops.
- ….. there are many more possible methods.
Again w.r.t to retention flops there were questions about, How many type of retention flops are available.
I have seen 3 types.
- Single save/restore pin retention latch (Slave latch being always on)
- Single pin balloon Latch
- Dual Pin balloon Latch
Advantages of Single Pin:
- Minimal area impact
- Single signal controls retention
Disadvantages of Single Pin:
- Performance Impact on the register
- Hold Time requirements for the input data
Advantage of Dual Pin:
- Minimal leakage power
- Minimal performance impact compared to the Single Pin design
- Minimal dependency on the clock for the control signals.
Disadvantages of Dual Pin:
- Area Impact
- More Complex System Design
- More Buffer Network and AON network required.