Top 10
RTL synthesis and other backend Interview Questions (with answers)
Q1: How would you speed up an ASIC design project by parallel computing? Which design stages can be distributed for pa…
Synthesis
Verification
Boosting RTL Verification with High-Level Synthesis
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creati…
Timing
Register re-timing
Register retiming is a sequential optimization technique that moves registers through the combinational logic gates of …
Verilog
Verilog rules that can save your breath !
This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rul…
Synthesis
Synthesis
Logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (…
Synthesis
Clock tree synthesis
Basics of Clock Tree Synthesis: The main idea is to balance the skew between endpoints. They are built with the followi…
Synthesis
Low power design
Primarily design for low power depends on the characteristics design being accomplished. If it is a multi-million gate …
Verification
Application Specific Integrated Circuit ( ASIC )
An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized f…