The Digital Electronics Blog

Interview Questions

RTL synthesis and other backend Interview Questions (with answers)

mg -9:35 PM BBC 1

ASIC

SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits

mg -2:47 PM BBC 1

C++

Boosting RTL Verification with High-Level Synthesis

mg -8:24 PM BBC 1

Re-Timing

Register re-timing

One Nanometer (Name changed) -11:48 AM BBC 1

Synthesis

Verilog rules that can save your breath !

One Nanometer (Name changed) -4:41 PM BBC 1

Synthesis

Synthesis

One Nanometer (Name changed) -10:53 AM BBC 1

Synthesis

Clock tree synthesis

One Nanometer (Name changed) -12:42 PM BBC 1

ASIC

Low power design

One Nanometer (Name changed) -2:22 AM BBC 1

ASIC

Application Specific Integrated Circuit ( ASIC )

One Nanometer (Name changed) -2:27 AM BBC 1