Displaying posts in the categorySynthesis
Synthesis articles
Top10
The RTL coding mistakes that cost the most power and area are the ones that make logic toggle when it does no useful work, or that build more hardware than the function needs. Clocks that run when registers hold their value, glitchy deep logic, oversized buses, resets on every flop and accidental latches are the usual culprits. Synthesis tools recover some of this, but they cannot undo an architecture or coding style that asks for waste. Below a…
by
Murugavel Ganesan
April 07, 2025
Synthesis
A multi-cycle path is a timing path that the design intends to take more than one clock cycle, so static timing analysis (STA) should check it against a later capture edge. A false path is a path that can exist structurally but is never required to carry a change that must be captured in a given time, so STA should not time it at all. Both are timing exceptions: constraints that override the default single-cycle check. Set correctly, they stop t…
by
Murugavel Ganesan
November 28, 2023
Verification
Zero-delay simulation runs a gate-level netlist with every gate and wire delay set to zero, so it checks that the synthesised logic does the right thing without checking when it does it. Use it early, after synthesis and before SDF-annotated timing simulation, to catch functional problems in the netlist quickly: wrong connectivity, reset and initialisation issues, X-propagation, and scan or test-mode behaviour. It cannot find setup or hold viola…
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Murugavel Ganesan
November 28, 2023
VHDL
Non-synthesizable VHDL is code that simulates correctly but that a synthesis tool cannot turn into gates and flip-flops, or turns into something different from what the simulator showed. The usual culprits are timing delays ( wait for , after ), initial values relied on in ASICs, processes with several different clock conditions, clock edges combined with else or wait , and testbench-only features such as file I/O. The fix is almost always to r…
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Murugavel Ganesan
September 13, 2013
Synthesis
The High Level Synthesis Blue Book is a comprehensive guide for designing hardware using C++. It is targeted to RTL designers that are currently using, moving, or planning to move, to an HLS design environment. Check the blog post by Thomas Bollaert and More here . The High-Level Synthesis Bluebook is available online by clicking here . Author Michael Fingeroff will also be hosting a free webinar on June 23rd where he will be presenti…
Synthesis
How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?
Synthesis
Re-timing reduces longest combinational logic paths by relocating some of the flip-flops, both logically and physically. How do you evaluate the effectiveness of re-timing, with existing tools and/or some of your own scripts? Comparing with useful clock skew is a plus.
Synthesis
This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. This can be done algorithmically (e.g. pattern matching) or in an ad-hoc fashion. You can verify your area saving, timing improvement and power consumption reduction after this step.
Synthesis
These nine RTL synthesis and backend interview questions cover the physical design topics interviewers return to most: parallelising the flow, reading timing reports, fixing violations, Elmore delay, wire sizing, zero-skew clock trees, in-place optimisation, ordering a clock and place-and-route flow, and design file sizes. Each question has the short answer an interviewer expects, followed by a fuller explanation. Several earlier explanations on…
VHDL
1. **For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the process. Please give a detailed reason and an exception to this statement.** *Reason:* The sensitivity list in a combinational process specifies the signals that, when changed, should trigger the execution of the process. In VHDL, a combinational process should be sensitive to all the signals that are read within the process t…
Synthesis
With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It's also production-proven with more physical design closure tools, advanced synthesis tools, ASIC libraries, and IP cores than any other formal verification tool. Many EDA tool vendors rely on Conformal ASIC as an independent standard within their regression suites to verify the results that their own tools produce. Key Feat…
Synthesis
Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementation platform, which delivers a two-fold speed-up in the synthesis and physical implementation flow. To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical tech…
by
Murugavel Ganesan
April 01, 2010
Verification
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creating bug-free RTL designs. This can be realized today by automating the generation of RTL from exhaustively verified C++ models. If done correctly , high-level synthesis (HLS) can produce RTL that matches the high-level source specification and is free of the errors introduced by manual coding.
Synthesis
It has been a while since we posted any puzzles or interview questions to tickle everyone's teeny brains. Recession has hit us in a big way and there seems to be a running drought in originality of the interview questions asked now-a-days. Even the ones shared on the various blogs that have cropped up these days are either ruthlessly copied or "massaged". Dont you think so? So to say, that while keeping the spirit or creativity and…
