Showing posts with the label Timing
Interview Questions

The effect of whitespace and aspect ratio on wirelength and timing

bymg - BBC1
False Path

High level analysis of false paths

bymg - BBC1
DFM

Probabilistic Timing Analysis

byMG - BBC1
Re-Timing

Register re-timing

byMG - BBC1
DVFS

Timing closure impacted by DVFS!!

byMG - BBC1
Interview Questions

Interview Question

byMG - BBC1
Gated clocks

Clock Latency & clock skew

byMG - BBC1
Frequency

Max Frequency calculation

byMG - BBC1
Frequency

Ways to increase frequency of operation

byMG - BBC1
ASIC

Application Specific Integrated Circuit ( ASIC )

byMG - BBC1
That is all