Timing
The effect of whitespace and aspect ratio on wirelength and timing
Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever…
Timing
Timing
High level analysis of false paths
Sometimes the delay through a component is dependent upon the values on signals. This is because different paths in the…
Timing
Probabilistic Timing Analysis
Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, pro…
Timing
Register re-timing
Register retiming is a sequential optimization technique that moves registers through the combinational logic gates of …
Timing
Timing closure impacted by DVFS!!
While designing systems with DVFS techniques, we need to look at the impact of temperature inversion on the performance…
Timing
Interview Question
Due to a miscommunication during design, you thought your circuit was supposed to have a supply voltage of 2.1 volts (t…
Timing
Clock Latency & clock skew
Clock latency means, the number of clock pulses required by the ckt to give out the first output. Generally we will obs…
Timing
Max Frequency calculation
In the simplest form: FF1 - combo - FF2 ( this is how things look physically for our consideration) Tmin = Tclk2Q (F…
Timing
Ways to increase frequency of operation
Check critical path and optimize it. Add more timing constraints (over constrain). pipeline the architecture to the max…
Verification
Application Specific Integrated Circuit ( ASIC )
An application-specific integrated circuit or ASIC comprises an integrated circuit (IC) with functionality customized f…