Interview Question - Testing
As time goes by, the average number of transistors on a chip is increasing faster than the number of input/output pins.…
As time goes by, the average number of transistors on a chip is increasing faster than the number of input/output pins.…
If we increase the supply voltage for a circuit, answer whether the short-circuiting current is most likely to increase…
Some software programming languages allow compilers to perform "short cut" or "short circuit" optim…
Due to a miscommunication during design, you thought your circuit was supposed to have a supply voltage of 2.1 volts (t…
Your group designs a microprocessor for use in cell phones and palmtop computers. You currently fabricate your chips on…
The average performance of products in your market segment triples every 36 months. Your design engineers have proposed…
When trying to validate the behavior of a circuit under boundary conditions, would you use coverage monitors or asserti…
When writing a specification for a circuit, the specification should be "obviously correct". What does this m…
What are the main differences between reference model testbenches and relational style testbenches? For what types of c…
For a system with 64 primary inputs, 1024 internal states, 6,120 combinational signals, and 14 primary outputs, how man…
Your task is to predict the maximum performance that you can achieve if you implement the following pseudocode in hardw…
The well-dressed marketing group just learned that a circuit you designed has undetectable faults. They are debating th…
You are on a team that is exploring power reduction techniques for a new design. The details of the design and implemen…
Dataflow diagrams are data-dependency graphs where the computation is divided into clock cycles. Purpose: Provide a dis…
For designs with significant control flow, algorithms can be described in software languages, flowcharts, abstract stat…
While you are eating lunch at your regular table in the company cafeteria, a vice president sits down and starts to tal…
Increasing clock speed without increasing power... The following are given: You need to increase the clock speed of a…
One day you are strolling the hallways in search of inspiration, when you bump into a person from the marketing departm…
If you were to compare a typical digital circuit from 5 years ago with a typical digital circuit today, would you find …
Assume that the timing diagram shows the limits of the allowed times (either minimum or maximum). For each of the terms…
If you have to write your own code (i.e. you do not have a library of memory components or a special component generati…
VHDL Disadvantages VHDL is verbose, complicated and confusing Many different ways of saying the same thing Constructs t…
Importance of Power and Energy: Laptops, PDA, cell-phones, etc —obvious! For microprocessors in personal computers, eve…
In digital logic design, there are different types of delay modeling. Some of the commonly used delay modeling techniqu…
May you get a clean bill of health from your dentist, your cardiologist, your gastro-enterologist, your urologist, your…
How long do you think DVDs have around? 20 years? 10 years? Actually, they have only been around for about seven years,…
Gate level simulation is used in the late design phase to increase the level of confidence about a design implementat…
This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rul…
Some web resources, references, labs, and slides. http://esd.cs.ucr.edu/
Logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (…
The history of the Verilog HDL goes back to the 1980s, when Gateway Design Automation developed Verilog-XL logic simula…
This is an Introductory & Comprehensive Verilog Course, which covers.. Modeling Designs for Digital Simulation. Mod…
Be a sponsor & Support this Blog Some of our Proud Sponsors: VLSIChipDesign Checkout how much a Text-Link is worth …
We are happy to invite you as a contributor to this blog in digital electronics. Of course, you can choose to be anonym…
After much awaited delay due to developments on the blogger in beta, i m happy to announce that i have successfully con…
Gate level simulation (GLS) is a technique for verifying the functionality and timing of a digital circuit after it has…
This article is about RTL in a Multi-Voltage environment and it's implication on verification. In the earlier …
Lets take a look at the various low power techniques in use today. I would classify them into 2 categories Structu…
Special cells are required for implementing a Multi-Voltage design. Level Shifter Isolation Cell Enable Level Shifter…
Before we start looking at implementing a Multi-Voltage design there are certain questions that need to be answered to …
In the last few weeks i have been quite busy with a lot of research on low power design. There are so many tutorial…
Multi-Vt placement/spacing concerns I was just thinking about most common concerns faced today in addressing leakage p…
By popular demand: Event simulation allows the design to contain simple timing information - the delay needed for a sig…
Last 2 weeks has witnessed a sudden surge in visitors and so i decided to continue my experiments for some more time wi…
I have found that this Blog has not attracted enough enthusiasts as expected. So due to lack of participation i m force…
What are the representations for, zero in 2's compliment the most positive integer that can be represented using…
You get the final chip back from the FAB. Now you do the smoke test(power up). Hopefully assuming that things are well …
Q: What is the significance of contamination delay in sequential circuit timing? Fact: 70-80% of designers who deal …