Gate Level Simulation, Part II: Unit Delay and Full SDF Timing

Gate level simulation comes in two main forms. Unit delay simulation runs the synthesised netlist with small fixed delays and no timing checks, to verify reset, scan and basic function quickly. Full timing simulation back-annotates real cell and wire delays and timing checks from an SDF file onto the post-layout netlist, to confirm the chip works with its real timing. This part of the series explains when each is used and how to set them up.

Gate level simulation is used in the late design phase to increase the level of confidence about a design implementation and to complement verification results created by static methods (formal verification and static timing analysis). It is slow, and its coverage of potential functional and timing problems depends heavily on the quality of the input stimulus, which cannot be guaranteed in a practical way.

Key takeaways

• GLS complements, but does not replace, equivalence checking and static timing analysis.
• Its real value is dynamic behaviour that static methods cannot see well, such as start-up and reset.
• Run a small, targeted set of tests with the most accurate timing available, rather than the full regression.
• Before layout there is no clock tree, so unit delay simulation with the specify blocks disabled is the usual choice.
• After layout, full timing simulation uses SDF back-annotation of path delays and timing checks.

Why gate level simulation is still needed

In addition to the medium to long run times needed to simulate comprehensive vector sets on large designs, GLS can never be exhaustive. In some cases, however, a gate level simulation can verify dynamic circuit behaviour that cannot be accurately verified with static methods. Typical examples:

• The start-up and reset phase of a chip, including reset synchronisers and the order in which blocks leave reset.
• X propagation through real library cells, which RTL simulation can hide or exaggerate.
• Asynchronous interfaces and clock domain crossings, where the real delays matter.
• Paths the timing constraints declared false or multicycle by mistake.
• Scan chain shift and capture, and power-aware behaviour such as isolation and retention.

To reduce the overall cycle time, only a minimum number of vectors should be simulated using the most accurate timing model available, that is, with parasitics extracted from the post-layout database.

Unit delay simulation

The netlist after synthesis but before routing does not yet contain the clock tree. Using SDF back-annotation at this step adds little, because the clock arrival times, which dominate many checks, are still ideal. Gate level simulation is still useful here: to verify the reset circuit and the scan chain, or to get switching activity for power estimation.

If no back-annotation is used, the simulator should use libraries with the specify block (which holds the timing arcs and timing checks) disabled, and with small distributed delays instead. The author's recommended defaults are:

Cell type	Default unit delay	Reason
Storage element (flop, latch)	10 ps	Gives every flop a clock-to-output delay larger than any unit-delay skew in the clock path, so downstream flops always capture the value from before the clock edge
Combinational gate	1 ps	Keeps event order realistic while adding almost no time to a logic path
Clock gating cell	0	Avoids skewing the gated clock against the ungated clock, which would cause false races

This is the most secure way to run unit delay simulation, and simulation memory use and speed are best when the specify block is disabled. The values are one sensible convention, not a standard; check what your library vendor's models expect. A rule of thumb: the storage element delay must be larger than the largest clock skew the unit delays can create, for example a clock that passes through a few muxes or buffers at 1 ps each before reaching some flops. If that skew could reach 10 ps, raise the flop delay. For more on this step, see Unit Delay Simulation: The Intermediate Step in GLS Explained.

Example: a cell model with both modes

Library models often use a compile-time switch to choose between unit delay and full timing. The simplified example below shows the idea. With UNIT_DELAY defined, the cells use 10 ps and 1 ps distributed delays and have no specify block; without it, the specify block provides path delays and a setup/hold check that SDF can overwrite.

`timescale 1ns/1ps
module DFFQX1 (input D, input CK, output reg Q);
`ifdef UNIT_DELAY
  // No specify block: small distributed delay on the storage element
  always @(posedge CK) Q <= #0.010 D;
`else
  always @(posedge CK) Q <= D;
  specify
    (posedge CK => (Q +: D)) = (0.120, 0.100);
    $setuphold(posedge CK, D, 0.050, 0.030);
  endspecify
`endif
endmodule

module AND2X1 (input A, input B, output Y);
`ifdef UNIT_DELAY
  assign #0.001 Y = A & B;
`else
  assign Y = A & B;
  specify
    (A => Y) = (0.040, 0.035);
    (B => Y) = (0.042, 0.037);
  endspecify
`endif
endmodule

module tb;
  reg a = 0, b = 0, clk = 0;
  wire y, q;
  AND2X1 g (.A(a), .B(b), .Y(y));
  DFFQX1 f (.D(y), .CK(clk), .Q(q));
  always #5 clk = ~clk;
  initial begin
    #1 a = 1; b = 1;
    @(posedge clk); #1;
    $display("t=%0t q=%b", $time, q);
    $finish;
  end
endmodule

Both modes print t=6000 q=1. The delay values in the specify blocks are illustrative, not from a real library.

Most commercial simulators also offer command-line options to ignore specify blocks, disable timing checks or force unit or zero delay globally (for example, +nospecify, +notimingcheck and +delay_mode_unit in Synopsys VCS). Option names differ between tools, so check your simulator's manual.

Full timing simulation (with SDF)

Full timing simulation is run by taking all timing delays from an SDF file. The SDF file is used to back-annotate values for propagation delays and timing checks onto the Verilog gate level netlist. SDF (Standard Delay Format) is standardised as IEEE 1497-2001; the file is written by the static timing tool from the post-layout netlist and extracted parasitics, so the simulation and the timing sign-off use the same delays.

In practice:

1. Generate the SDF from the sign-off STA tool for each corner you want to simulate, typically a slow corner for setup-type issues and a fast corner for hold-type issues.
2. Annotate it at time zero with the $sdf_annotate system task, naming the SDF file and the instance of the design in the testbench.
3. Check the annotation log. Unannotated cells or interconnects mean the netlist and the SDF do not match, and the results are not trustworthy.
4. Keep timing checks on, and handle known false violations, such as on synchroniser first stages, by disabling checks on those specific instances rather than globally.
5. Run the targeted tests: reset, start-up, clock switching, scan and a few functional smoke tests.

A worked sizing example

Illustrative numbers: if a full RTL regression is 5,000 tests and a post-layout SDF simulation runs 20 to 50 times slower than RTL for the same test, the full regression would take weeks. A targeted set of 30 to 50 GLS tests, run at two corners, finishes in a day or two and covers the dynamic behaviour that matters. The slowdown factor varies widely with the design and the tool; measure it on your own design.

Unit delay versus full timing

Aspect	Unit delay	Full timing (SDF)
Netlist	Post-synthesis, pre-route	Post-layout, with clock tree
Delays	Fixed small distributed delays	Back-annotated cell and interconnect delays
Timing checks	Off (specify block disabled)	On, from SDF
Main uses	Reset, scan, netlist function, power activity	Start-up, reset, asynchronous paths, constraint mistakes
Speed	Faster	Slowest

Common mistakes

• Running the full RTL regression at gate level. It costs a great deal and adds little; target the tests.
• Ignoring SDF annotation warnings. A partly annotated netlist gives false confidence.
• Turning timing checks off globally to silence synchroniser violations, which also hides real ones.
• Using a flop unit delay smaller than the unit-delay skew in the clock path, which creates false races between flops.

Related reading

• Gate Level Simulation, Part I: Introduction and Why GLS Is Still Needed
• Zero delay simulation, Why and When
• Different types of simulations
• Negative setup and hold time

FAQ

Is SDF back-annotation useful before layout?

It is possible with delays estimated from wire load models, but the clock tree is missing, so the results say little about real timing. Most teams use unit delay at this stage.

Why disable the specify block for unit delay simulation?

Without SDF, specify block values are only library defaults, and the timing checks can produce noise. Disabling them speeds up simulation and leaves the simple distributed delays in control.

How many GLS tests are enough?

There is no fixed number. Cover reset and start-up, every clock and reset domain, scan, low-power sequences and a few functional smoke tests at the key corners.