Interview Question - Low power

You are on a team that is exploring power reduction techniques for a new design. The details of the design and implementation are as follows:
  • The implementation technology has a nominal supply voltage of 1.8V and a threshold voltage of 0.4V.
  • At the nominal supply voltage, the design works at 500MHz.
  • The environment has two modes: high-bandwidth and low-bandwidth.
    • In the high-bandwidth mode, every clock cycle has valid data.
    • In the low-bandwidth mode, valid data arrives once every ten clock cycles (e.g. one clock cycle with valid data followed by ten cycles with invalid data.)
  • On average, the environment is in the high-bandwidth mode for 6 consecutive seconds and in the low bandwidth mode for 4 consecutive seconds.
  • The latency through the circuit is 3 cycles.
  • Short-circuit and leakage power are negligible.
One proposal for power reduction is to scale down the supply voltage when the circuit is in the low bandwidth mode.
Calculate how much saving can be achieved using the voltage scaling technique as a percentage of the original power consumption of the circuit.
  1. The scaled supply voltage is 1.2V.
  2. Supply scaling is done using a DC-DC converter whose power efficiency is 90% (i.e for every 100mW consumed in the converter, only 90mW are actually delivered to the circuit)
  3. The converter is inactive when the circuit operates at the nominal supply mode.
An alternative to voltage scaling is to use a clock gating scheme to turn the clock off when it is not needed.
Calculate the percentage of power that can be saved using this scheme.
  1. Clock gating circuit's area is 10% of the main circuit.
  2. The clock gating circuit has the same activity factor as the main circuit.
Which of the two techniques achieves a larger savings in power and how much more is it?
Your manager is proposing combining the two techniques in order to achieve additional power saving. Briefly discuss the possible limitations of this proposal.

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