Showing posts with label GLS. Show all posts
Showing posts with label GLS. Show all posts

Exclusive Interview on GLS (Gate level simulation)


A Verification engineer claiming mastery in Gate-level simulation is coming for an Interview.
Interviewer: Welcome
Job Seeker: thanks
(aliasing I for Interviewer and J for Job-seeker)
I : In your resume you had mentioned that are an expert in GLS(Gate-level simulation), how comfortable are you.
Read further Here

Gate Level Simulation, Part - II


Gate level simulation is used in the late design phase to increase the level of confidence about a design implementation and to complement verification results created by static methods (formal verification and static timing analysis). In addition to the disadvantages of medium to long run times to simulate comprehensive vector sets on large designs, the coverage of potential functional and timing problems highly depends on the quality of the input stimulus and cannot be guaranteed in a practical way. In some cases, however, a gate level simulation can help to verify dynamic circuit behavior that cannot be accurately verified with static methods. For e.g. the start up and reset phase of a chip. To reduce the overall cycle time, only a minimum amount of vectors should be simulated using the most accurate timing model available (parasitics extracted from post-layout database).

Unit Delay Simulation:
The netlist after synthesis, but before routing does not yet contain the clock tree. It does not make sense to use SDF backannotation at this step, but gatelevel simulation may be used to verify the reset circuit, the scan chain or to get data for power estimation. If no backannotation is used, simulators should use Libraries which have the specified block containing timing args disabled and using distributed delays instead. The default delay for a storage element at 10 ps, for a combinatorial gate 1 ps and a clock gating cell 0 is the most secure possibility to run unit delay simulation, and process size and performance are optimized if the specify block is disabled.

Full Timing Simulation (With SDF):
Simulation is run by taking full timing delays from sdf. The SDF file is used to back annotate values for propagation delays and timing checks to the Ver-ilog gate level netlist.

Comments are greatly appreciated.

Gate level simulation - Introduction


With wide acceptance of STA and Formal verification tools by the industry, one question still arises in the minds of many, "Why do we need gate-level simulation?"

The common reasons quoted by many engineers are simple.
  1. To check if reset release, initialization sequence, and boot-up is proper.
  2. Since Scan insertions occur during and after synthesis, they are not checked by simulations.
  3. STA does not analyze asynchronous interfaces. This is used to validate the constraints used in STA and LEC. Static verification tools are constraint-based and they are only as good as the constraint used. Unchecked use of wildcards and late design changes not propagating to constraints or incorrect understanding of the design require validation of these constraints.
  4. Unwarranted usage of wild cards in static timing constraints set false and multi-cycle paths where they don't belong. This can also be due to design changes, misunderstanding or typos.
  5. Usage of create_clock instead of using create_generated_clock between clock domains.
  6. For switching factor to estimate power.
  7. X's in RTL sim can be pessimistic or optimistic. Any unintended dependencies on initial conditions can be found through GLS.
  8. Design changes, a wrong understanding of the design can lead to incorrect false paths or multicycle paths in the constraints.
  9. Can be used to study the activity factor for power estimation.
  10. It's an excellent feel-good quotient that the design has been implemented correctly.
Some design teams use GLS only in a zero-delay, ideal clock mode to check that the design can come out of reset cleanly or that the test structures have been inserted properly. Other teams do fully back annotated simulation as a way to check that the static timing constraints have been set up correctly.

GLS is also used to collect switching activity for power estimation and correlation, to verify the integration of digital and analog netlists, required to simulate ATPG patterns, generate ATE test vectors, validate EDA tool flow change while moving from one vendor’s sign off tool to another, validate that RTL simulations were not having any undesired force statements from the test bench and masking bugs.

In all cases, getting a gate-level simulation up and running is generally accompanied by a series of challenges so frustrating that they invoke a shower of adjectives. There are many sources of trouble in gate-level simulation. This series will look at examples of problems that can come from your library vendor, problems that come from the design, and problems that can come from synthesis. It will also look at some of the additional challenges that arise when running a gate-level simulation with back annotated SDF.