Showing posts with label gate-level simulation. Show all posts
Showing posts with label gate-level simulation. Show all posts

Unit delay simulation - an intermediate step in Gate level simulation!

This is an intermediate step during Gate level simulation!

Unit delay simulation operates on the assumption that all the elements in a circuit posses identical delays. This has an advantage that it can be setup early in the flow when the post layout netlist is ready but before the SDFs are not available which could be due to the fact that the design is not timing clean and is in the process of being timinh closed.

Primarily Unit delay sims help in ironing out any possible simulation synthesis mismatches due to delta delay issues and so widely used in the industry. But this kind of simulation should not be used to generate test stimuli. If done, this will give a false sense of security as the timing for the actual circuit will not resemble the results shown by the unit delay simulation. Another major disadvantage of unit delay simulation is that since the elements have non-zero delay, the design cannot be rank-ordered for simulation and hence unnecessary evaluation of elements several times in a same period can happen.

Unit delay simulation is very useful for FPGAs and CPLDs. Since these are fixed array circuits of rows and columns with identical elements that may be a NAND or NOR gate or a collection of resistors and transistors. Switching elements connected in this way usually have the same switching speed in which case unit delay sims become very meaningful. If the switching speeds are integral multiples of one another unit delay sims can still be effectively implemented.

Different types of simulations!

Functional simulation: Simulation of a design description. This is also called spec simulation or concept simulation. This is usually done at the highest level and in the beginning of the project.

Behavioral simulation: Simulation of digital circuit described in HDLs like verilog or VHDL. We simulate the behavior described in these language based designs. This the second step.

Static timing analysis: This tells us "What is the longest delay in my circuit?" Timing analysis finds the critical path and its delay. Timing analysis does not find the input vectors that activate the critical path. Done after synthesis, this is the third step.

Gate-level simulation: Differences between functional simulation, timing analysis, and gate level simulation. In this type of simulation the delays after the post layout stage are back annotated to the design using SDF and simulated. This gives close to a real chip simulation performance. This is the final step.

Transistor-level or circuit-level simulation: Mainly for mixed mode(mixed signal) circuits. For mixed mode circuit we must verify complete design on transistor level. This is an intermediate step based on how the design is setup and the flow.
Simulation conclusion:
  1. Behavioral simulation can only tell you only if your design will not work.
  2. Pre-layout simulation estimates your design performance.
  3. Finding a critical path is difficult because you need to construct input vectors to exercise the right paths.
  4. Behavioral simulation and Static timing analysis is the most widely used form of simulation.
  5. Formal verification compares two different representations. It cannot prove your design will work.
  6. Switch-level simulation can check the behavior of circuits that may not always have nodes that are driven or that use logic that is not complementary.
  7. Transistor level simulation is used when you need to know the analog, rather than the digital, behavior of circuit voltages.
  8. Trade-off in accuracy against run time.