- Purpose:
- Provide a disciplined approach for designing datapath-centric circuits.
- Guide the design from algorithm, through high-level models, and finally to RTL code for the datapath and control circuitry.
- Estimate area and performance.
- Make tradeoffs between different design options.
- Background
- Based on techniques from high-level synthesis tools.
- Some similarity between high-level synthesis and software compilation.
- Each dataflow diagram corresponds to a basic block in software compiler terminology.
To be completed..
Area Estimation:- Maximum number of blocks in a clock cycle is the total number of that component that are needed.
- Maximum number of signals that cross a cycle boundary is the total number of registers that are needed.
- Maximum number of unconnected signal tails in a clock cycle is the total number of inputs that are needed.
- Maximum number of unconnected signal heads in a clock cycle is the total number of outputs that are needed.
To be completed..
Performance Estimation:To be completed..
Design Analysis:To be completed..
Area / Performance Tradeoffs:
To be completed..
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