Hierarchy and Power Gating

A scalable approach to chip architecture is essential and valuable since a SOC design today often becomes a component in an even larger chip in subsequent product generations.

To support this portability, module boundaries must be enforced at the power domains level. That is, a given module should belong to a single power domain, not split across several domains. Some tools and flows support RTL process by RTL process assignment to power domains, but this leads to much more complicated implementation and analysis. Clean visibility of the boundaries of a power gated block is key to having a clean, top-down implementation and verification flow.

Although one can in theory nest power gated modules arbitrarily within power gated subsystems which are in turn nested on a shared switched power rail, there are considered benefits in not creating multiple levels of power switching fabric. Power gating is intrusive and ass in some voltage drop and degradation of performance. Cascading multiple voltage drops can lead to unacceptable increases in delay. Even if the design is representeted as hierarchical at the architectural level, the implementation is improved if this is mapped on to a single level of power gating at implementation.

Recommendations:

• Map power gated regions to explicit module boundaries.
• When partitioning a hierarchical power gating design ensure that the power gating control terms can be mapped back to a flat switching fabric.

Pitfalls:

• Avoid control signals passing through power gated or power down regions to other power regions that not hierarchically switched with the first region.
• Avoid excessively fine power gating granularity unless absolutely required for aggressive leakage power management. Every interface adds implementation and verification challenges and complicates the system level production test challenges.
• Avoid a power gating system of more that one or two levels.