Non-Synthesizable VHDL Code


RTL Synthesis is done by matching high level code against templates or patterns. It is important to use idioms that your synthesis tool recognizes. If you aren’t careful, you could write code that has the same behavior as one of the idioms, but which results in inefficient or incorrect hardware.





Most synthesis tools agree on a large set of idioms, and will reliably generate hardware for these idioms. This post is based on the idioms that Synopsys, Xilinx, Altera, and Mentor Graphics are all able to synthesize. We consider combinational loops to be unsynthesizable. Although it is obviously possible to build a circuit with a combinational loop, in most cases the behaviour of such a circuit is undefined.

Initial Values
Initial values on signals (UNSYNTHESIZABLE)
signal bad_signal : std_logic := ’0’;
Reason: In most implementation technologies, when a circuit powers up, the values on signals are completely random. Some FPGAs are an exception to this. For some FPGAs, when a chip is powered up, all flip flops will be ’0’. For other FPGAs, the initial values can be programmed.

Wait For
Wait for length of time (UNSYNTHESIZABLE)
wait for 10 ns;
Reason: Delays through circuits are dependent upon both the circuit and its operating environment, particularly supply voltage and temperature.

Different Wait Conditions
wait statements with different conditions in a process (UNSYNTHESIZABLE)
-- different clock signals
process
begin
wait until rising_edge(clk1);
x <= a;
wait until rising_edge(clk2);
x <= a;
end process; 

-- different clock edges
process
begin
wait until rising_edge(clk);
x <= a;
wait until falling_edge(clk);
x <= a;
end process; 

Reason: Processes with multiple wait statements are turned into finite state machines. The wait statements denote transitions between states. The target signals in the process are outputs of flip flops. Using different wait conditions would require the flip flops to use different clock signals at different times. Multiple clock signals for a single flip flop would be difficult to synthesize, inefficient to build, and fragile to operate.

Multiple “if rising edge”s in Same Process
Multiple if rising edge statements in a process (UNSYNTHESIZABLE)
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
end if;
if rising_edge(clk) then
q1 <= d1;
end if;
end process;
Reason: The idioms for synthesis tools generally expect just a single if rising edge statement in each process. The simpler the VHDL code is, the easier it is to synthesize hardware. Programmers of synthesis tools make idiomatic restrictions to make their jobs simpler.

“if rising edge” and “wait” in Same Process
An if rising edge statement and a wait statement in the same process (UNSYNTHESIZABLE)
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
end if;
wait until rising_edge(clk);
q0 <= d1;
end process;
Reason: The idioms for synthesis tools generally expect just a single type of flop-generating statement
in each process.

“if rising edge” with “else” Clause
The if statement has a rising edge condition and an else clause (UNSYNTHESIZABLE).
process (clk)
begin
if rising_edge(clk) then
q0 <= d0;
else
q0 <= d1;
end if;
end process;
Reason: Generally, an if-then-else statement synthesizes to a multiplexer. The condition that is tested in the if-then-else becomes the select signal for the multiplexer. In an if rising edge with else, the select signal would need to detect a rising edge on clk, which isn’t feasible to synthesize.

“if rising edge” Inside a “for” Loop
An if rising edge statement in a for-loop (UNSYNTHESIZABLE-Synopsys)
process (clk) begin
for i in 0 to 7 loop
if rising_edge(clk) then
q(i) <= d;
end if;
end loop;
end process;
Reason: just an idiom of the synthesis tool.
Some loop statements are synthesizable. For-loops in general are described in the VHDL cookbook by Ashenden. For the curious reader, the above code is an 8-bit serial-to-parallel converter. The signal d is the serial data and q is the parallel data. On each clock cycle, d is copied into one of the bits of q.

For the synthesizable alternatives, please discuss/leave comments below.


{ 7 Reactions ... read them below or write one }

Bob said on September 13, 2013 at 4:28 PM

A synthesizable alternative to an if rising edge statement in a for-loop is to put the if-risingedge outside of the for loop.

process (clk)
begin
if rising_edge(clk) then
for i in 0 to 7 loop
q(i) <= d;
end loop;
end if;
end process;

--//Peace

Anonymous said on September 13, 2013 at 4:29 PM

Clocked for-loops are not synthesizable, but are very useful in simulation, particular to generate test vectors for test benches.

himu said on September 19, 2013 at 8:39 PM

non-synthesizable codes are not translatable in hardware.......so why do we still use it?

Murugavel Ganesan said on September 20, 2013 at 11:19 AM

@ Himu, Such code is used as behavioral codes in RTL modelling. Mostly used for testbench components for functional simulation.

himu said on September 21, 2013 at 12:52 PM

thnx a lot @Ganesan

Jack said on September 23, 2013 at 5:08 PM

This is the synthesizable alternative to the the wait statement in a for loop.

process
begin
-- output values from 0 to 4 on i
-- sending one value out each clock cycle
i <= to_unsigned(0,4);
wait until rising_edge(clk);
while (4 > i) loop
i <= i + 1;
wait until rising_edge(clk);
end loop;
end process;

Murugavel Ganesan said on September 24, 2013 at 7:27 AM

Some coding styles are synthesizable and might produce desirable hardware with a particular synthesis tool, but either be unsynthesizable or produce undesirable hardware with another tool.

1. variables
2. level-sensitive wait statements
3. missing signals in sens list

If you are using a single synthesis tool for an extended period of time, and want to get the full power of the tool, then it can be advantageous to write your code in a way that works for your tool, but might produce undesirable results with other tools.

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