Showing posts with label Clock Networks. Show all posts
Showing posts with label Clock Networks. Show all posts

Clock network design


Clock network is usually formed by top-level mesh/network and bottom-level Steiner minimum trees. The objective of clock network design is 1.) minimum or bounded skew, 2.) minimum delay, 3.) bounded process variation. Can we compare different clock topologies, or, how can we evaluate the effectiveness of clock boosters and feedback loops?

Clock driver input alignment


Modern clock networks include several drivers in which delays are affected by the timing of their input signal transitions. How do you find out the input alignment of clock network drivers which leads to worst case driver gate delays?