Verilog module that uses Euclid's algorithm to iteratively compute the greatest common divisor of two 16-bit unsigned integer values Ain and Bin where Ain ≥ Bin.
module gcd (clk,start,Ain,Bin,answer,done);
input [15:0] Ain,Bin;
output reg [15:0] answer;
output reg done;
reg [15:0] a,b;
always @ (posedge clk)
done <= 1;
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