Digital "Greatest Common Divisor (GCD)" - Euclid’s algorithm

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Verilog module that uses Euclid's algorithm to iteratively compute the greatest common divisor of two 16-bit unsigned integer values Ain and Bin where Ain ≥ Bin.

module gcd (clk,start,Ain,Bin,answer,done);
input clk,start;
input [15:0] Ain,Bin;

output reg [15:0] answer;

output reg done;


reg [15:0] a,b;

always @ (posedge clk)
begin
if (start)
begin
a <= Ain; b <= Bin; done <= 0;
end
else if (b == 0)
begin
answer <= a;
done <= 1;
end
else if (a > b)
a <= a – b;
else
b <= b – a;
end
endmodule

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  2. This will go into infinite loop, e.g. if a=0 and b=5

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