Interview Questions (Intel)

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# Have you studied buses? What types?
Ans: 1. Processor-Memory Bus, I/O Bus, System Bus, Backplane Bus.

# Have you studied pipelining? List the 5 stages of a 5 stage pipeline. Assuming 1 clock per stage, what is the latency of an instruction in a 5 stage machine? What is the throughput of this machine ?
Ans: A method of executing a sequence of instructions in a single processor so that subsequent instructions in the sequence can begin execution before previous instructions complete execution.

5 Stages:
1. fetch instructions from memory
2. read registers and decode the instruction
3. execute the instruction or calculate an address
4. access an operand in data memory
5. write the result into a register

Latency: It's the amount of time between when the instruction is issued and when it completes. 6 Clock Cycles.
Throughput: The number of instructions that complete in a span of time.

# How many bit combinations are there in a byte?
Ans: 256

# For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

# Explain the operation considering a two processor computer system with a cache for each processor.

# What are the main issues associated with multiprocessor caches and how might you solve them?

# Explain the difference between write through and write back cache.

# Are you familiar with the term MESI?

# Are you familiar with the term snooping?
Ans: Looking into a packet to obtain information. Usuall used to verify data at the output a logic core with inbuilt snoopers.

# Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that results in heads.

# In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

# You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

# What is the difference between = and == in C?
Ans: Assignment and Equality operators.

# Are you familiar with VHDL and/or Verilog?

# What types of CMOS memories have you designed? What were their size? Speed?
Ans: SRAM, 10Kbits, 50 Mhz.

# What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

# What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?

# Process technology? What package was used and how did you model the package/system? What parasitic effects were considered?

# What types of high speed CMOS circuits have you designed?
Ans: FF's and Latch based Fast Mutipliers.

# What transistor level design tools are you proficient with? What types of designs were they used on?
And: PSPICE, MAGIC layout system, CMOS mutiplier chip, 0.8 u tech.

# What products have you designed which have entered high volume production?
Ans: TOE.

# What was your role in the silicon evaluation/product ramp? What tools did you use?

# If not into production, how far did you follow the design and why did not you see it into production?

# Explain how a MOSFET works.

# Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width © considering Channel Length Modulation

# Explain the various MOSFET Capacitances & their significance

# Draw a CMOS Inverter. Explain its transfer characteristics

# Explain sizing of the inverter

# How do you size NMOS and PMOS transistors to increase the threshold voltage?

# What is Noise Margin? Explain the procedure to determine Noise Margin?

# Give the expression for CMOS switching power dissipation.

# What is Body Effect?

# Describe the various effects of scaling?

# Give the expression for calculating Delay in CMOS circuit
Ans: Tp = (tphl+tplh)/2, where tphl = 0.69 Req C & tplh = 0.69 Req C where C is the external capacitance made up of the diffusion capactiances of the drain and the fanout capacitance of the gates, Req is the equivalent resistance which could be either integrated if we are actually talking about in the resistive region or can be calculated in the saturation region.

# What happens to delay if you increase load capacitance?
In digital circuits, the delay of a gate or a circuit is influenced by various factors, and one significant factor is the load capacitance. Load capacitance refers to the total capacitance that a gate or a circuit has to drive, and it includes the capacitance of the connected wires, the input capacitance of the subsequent gates, and any other capacitive loads.

The delay of a gate or a circuit can be broadly represented by the following formula:

Delay = Propagation Delay + Contamination Delay

Now, let's discuss how increasing load capacitance affects the delay:

Propagation Delay:
Propagation delay is the time it takes for the signal to propagate through the gate. It is directly influenced by the load capacitance.
As the load capacitance increases, the time it takes to charge or discharge the capacitive load also increases. This leads to an increase in the propagation delay.
Contamination Delay:
Contamination delay is the time it takes for the output to start changing after the input has changed. It is less affected by load capacitance.
In some cases, a higher load capacitance might lead to a slight increase in contamination delay, but the impact is generally smaller compared to the effect on propagation delay.
Overall Delay:
The overall delay of the circuit is the sum of propagation delay and contamination delay.
Increasing load capacitance increases the overall delay of the circuit. This is particularly important in high-speed digital circuits, where minimizing delay is crucial for achieving desired performance.
Fan-Out Effect:
Load capacitance is also related to the concept of fan-out, which is the number of gates that a gate output is connected to. Higher fan-out increases the load capacitance, and as a result, it can increase the overall delay. 
In summary, increasing load capacitance in a digital circuit generally leads to an increase in the overall delay. Designers need to consider load capacitance carefully, especially in high-speed applications, to ensure that the circuit meets timing requirements and operates within the desired performance specifications. Techniques such as buffering or using lower-capacitance technologies may be employed to mitigate the impact of increased load capacitance on circuit delay.

# What happens to delay if we include a resistance at the output of a CMOS circuit?
Ans: cause power dissipiation.

# What are the limitations in increasing the power supply to reduce delay?
Ans: Increase in Dynamic Power dissipation

# How does Resistance of the metal lines vary with increasing thickness and increasing length?
Ans: Resistance is directly propotional to length and inversly propotional to area, hence higher metals have lesser resistance and Increasing L increases the resistance.

# What happens if we increase the number of contacts or via from one metal layer to the next?
Ans: Increase in contact resistance.

# Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times

# Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?

# Draw the stick diagram of a NOR gate. Optimize it.

# For CMOS logic, give the various techniques you know to minimize power consumption

# What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus

# Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?

# In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?

# Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)

# Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram

# Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
Ans: NMOS passes clean zero and a bad one while PMOS passes clean 1 and bad zero(Ref: Kamran)

# For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD

# Draw a 6-T SRAM Cell and explain the Read and Write operations

# Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)

# What happens if we use an Inverter instead of the Differential Sense Amplifier?

# Draw the SRAM Write Circuitry

# Approximately, what were the sizes of your transistors in the SRAM cell? How did you arrive at those sizes?

# How does the size of PMOS Pull Up transistors (for bit & bit- lines) affect SRAM’s performance?

# What’s the critical path in a SRAM?

# Draw the timing diagram for a SRAM Read. What happens if we delay the enabling of Clock signal?

# Give a big picture of the entire SRAM Layout showing your placements of SRAM Cells, Row Decoders, Column Decoders, Read Circuit, Write Circuit and Buffers

# In a SRAM layout, which metal layers would you prefer for Word Lines and Bit Lines? Why?

# How can you model a SRAM at RTL Level?

# What’s the difference between Testing & Verification?

# For an AND-OR implementation of a two input Mux, how do you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes? (You can expect a circuit with some redundant logic)

# What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How do you avoid Latch Up?

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  1. Can somebody post more solutions to this list. -- thanks, ravi

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