Types of Timing Verification: Dynamic Simulation vs Static Timing

There are two main types of timing verification: dynamic timing, where the design is simulated with real delays and a set of test vectors, and static timing analysis (STA), where the tool adds up the delays along every path and compares them with the clock without any vectors. STA is fast and complete for synchronous logic, so it is the sign-off method for most digital chips. Dynamic timing simulation is slower and only as good as its vectors, but it is still useful for asynchronous interfaces, clock domain crossings and checking that the timing constraints themselves are right.

This post compares the two, explains how process, voltage and temperature change delays, and walks through how delays are estimated before layout, from wire load models to physical synthesis.

Key takeaways

• Dynamic timing simulates the gate-level netlist with back-annotated delays; coverage depends entirely on the test vectors.
• Static timing checks every structural path for setup and hold without vectors, and is far faster than full timing simulation.
• STA analyses false paths too, unless the designer declares them, which is why correct constraints matter as much as the tool.
• Delays vary with process, voltage and temperature (PVT), so timing is checked at several corners: slow corners for setup, fast corners for hold.
• Pre-layout delay estimates have moved from statistical wire load models to placement-aware (physical) synthesis, because wire delay now dominates.

Dynamic timing verification

In dynamic timing verification the design is simulated in full timing mode. The gate-level netlist is annotated with cell and wire delays, usually from a Standard Delay Format (SDF) file written by the timing tool, and the simulator checks setup and hold windows at every flip-flop as the vectors run.

• Not all possibilities are tested, because the result depends on the input test vectors. A path that the vectors never exercise is never checked.
• Simulations in full timing mode are slow and need a lot of memory. On a large design a gate-level timing run can take many times longer than an RTL run.
• It is the best method to check asynchronous interfaces or interfaces between different timing domains, because it shows what the logic actually does when data arrives near a clock edge, including X propagation from timing violations.

Today gate-level timing simulation is used selectively: for reset and power-up sequences, asynchronous interfaces, scan and test modes, and as a cross-check that no false path or multicycle constraint has hidden a real failure.

Static timing analysis

In static timing the delays over all paths are added up and compared with the required time set by the clock. The tool does not need vectors, because it does not care what value the data has, only how long the slowest and fastest changes take to arrive.

• All possibilities are verified without the need for test vectors, including false paths. A false path is a path that exists in the netlist but can never carry a meaningful transition in operation. STA will report it as a violation unless the designer declares it with a constraint such as set_false_path.
• It is much faster than simulation. In the original version of this post (2005) the comparison was hours as opposed to days, and the gap has only grown since.
• It is not good with asynchronous interfaces or interfaces between different timing domains. STA can only time paths between related clocks. Crossings between unrelated clocks are normally cut from STA and checked instead with dedicated clock domain crossing (CDC) tools and synchroniser rules.

Worked example: setup and hold slack

The numbers below are illustrative, not from a real library. A register-to-register path runs on a 2.0 ns clock (500 MHz).

Item	Setup check (slow corner)	Hold check (fast corner)
Launch flip-flop clock to Q	0.15 ns	0.10 ns
Combinational logic	1.40 ns	0.05 ns
Wire delay	0.15 ns	0.02 ns
Data arrival time	1.70 ns	0.17 ns
Capture clock skew (capture later than launch)	+0.05 ns	+0.05 ns
Clock uncertainty	0.10 ns	0.05 ns
Setup or hold time of capture flip-flop	0.10 ns	0.05 ns
Required time	2.0 + 0.05 - 0.10 - 0.10 = 1.85 ns	0.05 + 0.05 + 0.05 = 0.15 ns
Slack	1.85 - 1.70 = +0.15 ns (met)	0.17 - 0.15 = +0.02 ns (met)

Two points follow. The setup check uses the clock period and the slowest delays; the hold check does not use the period at all and uses the fastest delays. Positive skew helps setup and hurts hold. A static timing tool repeats this arithmetic for millions of paths and every corner in a few hours.

Dynamic and static timing compared

Aspect	Dynamic timing simulation	Static timing analysis
Needs test vectors	Yes	No
Coverage	Only the paths the vectors exercise	Every structural path, including false paths unless constrained
Run time and memory	Slow, memory hungry	Much faster
Asynchronous and multi-clock interfaces	Good: shows real behaviour	Poor: crossings are usually excluded and checked with CDC tools
Functional checking	Yes, timing and function together	No, timing only
Main risk	Missed paths through weak vectors	Wrong or missing constraints

How process, voltage and temperature change delays

Timing delays are determined by the layout, but they vary with temperature, voltage and process (PVT). A cell from a fast wafer, at high supply voltage and low temperature, can switch much faster than the same cell from a slow wafer at low voltage and high temperature.

• The ASIC vendor supplies factors based on their technology to allow verification under different environments. These have generally been called best and worst case military, industrial and commercial. The nominal delay is multiplied by a factor chosen by the designer to best represent the final operating conditions or the system requirements.
• Some vendors characterise their technology at all the required operating points instead, so each corner has its own library rather than a scaling factor. This is now the normal practice: one Liberty library per PVT corner.
• Worst case military results in the longest delays and thus the most setup time violations.
• Best case commercial results in the shortest delays and thus the most hold time violations.

The standard temperature grades are commercial 0 to 70 °C, industrial -40 to 85 °C and military -55 to 125 °C. Automotive parts use the AEC-Q100 grades, for example grade 1 at -40 to 125 °C.

One update to the original rule: the statement that the hottest corner is always the slowest held for the technologies of 2005. At many advanced low-voltage nodes, cells can be slower when cold because of temperature inversion, so the worst setup corner may be at the low end of the temperature range. Sign-off therefore checks both temperature extremes rather than assuming which one is worse.

Corner (typical name)	Process	Voltage	Temperature	Mainly used for
Slow (SS)	Slow transistors	Minimum	Maximum, and minimum where inversion applies	Setup
Typical (TT)	Nominal	Nominal	Room or nominal	Power estimates, reference
Fast (FF)	Fast transistors	Maximum	Minimum, and maximum where inversion applies	Hold

On top of the global corners, modern STA adds on-chip variation (OCV) derates, so that the launch and capture paths of the same check are not assumed to be equally fast. Advanced forms such as AOCV and POCV make the derate depend on path depth or on statistical cell variation.

Calculating an estimated delay before layout

Before layout exists, the designer and the synthesis tool still need a delay estimate for each path. The main ideas are below.

• In synchronous design, timing should be considered when choosing the algorithm. Avoid long paths before a register stage; pipelining a deep adder or multiplier early is cheaper than fighting it at layout.
• Synthesis is constraint driven. The synthesis tool generates the circuit using timing as a critical factor, which is why clock definitions and input and output delays must be written before the first run.
• The libraries from the vendor include the intrinsic delays of the cells, along with how each delay changes with input slew and output load.
• The wire load model is a statistically based estimate, provided by the vendor for the target die size, of the load that a certain fanout will produce. This load is then used to calculate the propagation delay.
• Floorplanning lets information about the placement of cells be used in timing estimation. Because routing usually follows the placement closely, placement is the dominant factor in wire delay.
• Rather than trusting a wire load model, which becomes less accurate as interconnect delay starts to dominate, the floorplan can be used. This can give very accurate timing information provided the floorplan drives the layout.
• A floorplan restricts the layout tool, often resulting in less efficient use of the silicon die. As it is a manual process, human error can become a factor, and for this reason some vendors did not offer floorplanning in their design flow.
• Physical synthesis was a new synthesis strategy when this post was first written. The synthesis tool places the cells and calculates estimated delays based on the minimum distance in the x-y plane.
• If the timing fails, a new placement is tried or different cells are synthesised.
• The tool outputs the netlist and the placement file, which the layout tool then uses as its starting point.

Physical synthesis is now the mainstream approach for advanced nodes. Synopsys (Design Compiler Topographical and its successors) and Cadence (Genus with physical awareness) both offer placement-aware synthesis, so that the timing seen in synthesis correlates with what place and route will produce.

Wire load models

• A wire load model is a statistical estimate of the load, based on fanout and block size.
• If the estimate is too conservative, high-drive cells are used and more power and area are consumed. If the estimate is too optimistic, there will be widespread timing problems after layout.
• The main drawback is that no information about placement or routing is available, so two nets with the same fanout get the same estimate even if one is local and one crosses the die.

For a small block in an older technology a wire load model can still be good enough. For large blocks at deep submicron nodes, where a long wire can contribute more delay than the gates it connects, placement-aware estimates are needed.

From estimate to sign-off

1. Synthesis: wire load models or physical synthesis give the first timing picture.
2. Placement and clock tree synthesis: real cell locations and real clock skew replace the ideal clock.
3. Routing and extraction: the actual wires are extracted into resistance and capacitance, typically as a SPEF file.
4. Sign-off STA: tools such as Synopsys PrimeTime or Cadence Tempus check every mode and corner with the extracted parasitics.
5. Gate-level timing simulation: the same delays, written out as SDF, are used for selected dynamic checks.

Common mistakes

• Treating a clean STA report as proof that the design works, when false path or multicycle constraints were added to make violations go away.
• Timing clock domain crossings in STA, or cutting them without checking the synchronisers with a CDC tool.
• Checking setup only at the slow corner and hold only at the fast corner without considering temperature inversion or OCV.
• Over-constraining synthesis with a pessimistic wire load model and paying for it in power and area.

Frequently asked questions

Is static timing analysis enough on its own?

For synchronous logic it is the sign-off method, but it only checks what the constraints describe. Asynchronous interfaces, clock domain crossings and the correctness of the constraints still need other checks, such as CDC analysis, constraint review and selected gate-level simulation.

Why does STA report false paths?

Because it works on the structure of the netlist, not on the logic values that can occur. A path that can never be sensitised in operation looks like any other path until the designer declares it false.

Which corner is used for hold checks?

Mainly the fast corner, where delays are shortest. Hold checks are also run at other corners with OCV derates, because launch and capture paths can vary differently.

Are wire load models still used?

They are still available in many libraries and can be adequate for small blocks or older nodes, but most advanced-node flows use placement-aware synthesis instead.