Displaying posts in the categoryVerification
Wireless
This opening is in Bangalore, India and the company is looking forward to close it at the earliest Job Description: 1. About 5-7 years of experience in functional verification with at least 3-4 years in HVL's like E language/specman and System Verilog. 2. Good experience at both module and sub-system/SOC level verification 3. Good knowledge of Verilog/VHDL 4. Good knowledge of UVM/eRM methodology 5. Should have developed complete test ben…
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Murugavel Ganesan
March 20, 2012
Verification
The topic of "peer code review" is a widely discussed topic in the context of design verification. I remember the times very early in my career when my code was reviewed. There were lots of positives occasionally with some negatives which i have improved over time. What is that people look for in a code review and what is the value add? Is it the most easy and powerful way of hunting down issues and avoid reproducing them by educating …
Verification
Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play. In our earlier post we reflected on the Cadence rollout of Palladium XP, a verification computing platform that unifies acceleration capabilities from the Incisive Xtreme product line with Incisive Palladium emulation, incorporating some of the strongest capabilities from each platform. You can read the press release her…
Verification
Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/ software environment faster and produce better qualit…
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Murugavel Ganesan
April 27, 2010
Verification
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is used in a wide variety of memory system designs for computers and embedded systems. This DRAM memory primer provides an overview of DRAM concepts, presents potential future DRAM developments and offers an overview for memory design improvement through verification.
Verification
This webcast highlights The SPIRIT Consortium's new IP-XACT 1.4 specification which expands the range of IP that can be used in an IP-XACT Design Environment and targets new applications, specifically those dealing with transactional modeling and advanced verification methodologies. IP-XACT 1.4 benefits include documentation of all aspects of IP using XML databook format, documentation of models in a quantifiable and language- independent …
Verification
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creating bug-free RTL designs. This can be realized today by automating the generation of RTL from exhaustively verified C++ models. If done correctly , high-level synthesis (HLS) can produce RTL that matches the high-level source specification and is free of the errors introduced by manual coding.
Verification
Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart design as well as an understanding of metastability and other physical behaviors. This white paper discusses the nature of CDC errors and presents a powerful solution that aids in their detection and removal.Note: By clicking on the above link, this paper will be emailed to your TechOnline log-in address by Mentor Graphics.
Verification
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the hard way, by trial, error, experience, and long days and nights. These excerpted chapters, part1 , part2 , part3 from a book, Debugging: The 9 Indispensable Rules for Finding Even the Most Elusive Software and Hardware Problems , published by AMACOM Books is informative and a logical introduction to the skill and art of begging…
Verification
According to Mitch Weaver, corporate vice president for front-end verification at Cadence, the e verification language is not only still alive but is thriving and growing. In this pre-DVCon interview , he answers questions about Cadence and industry support for the e language and the Specman/ e verification environment, as provided by Incisive Specman Elite and Incisive Enterprise Simulator XL.[Via: Industry Insights ]
Verification
In this article Richard Goering talks about a software bug in Toyota Prius 2005 and after 5 years even after a through study by three of Toyota engineers on this issue did not help the company learn any lessons. He also talks about model-based verification which the original presentation talks about and how a formalized methodology for verification can help alleviate issues that may arise later in the field. Clearly a must read article!
Verification
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cannot be ignored or hind-sighted and they are part of the chip design process itself. You may also have known or learnt that there is always a productivity gap, the significance of verification, the very famous pentium bug, the moore's law, that verification cannot be done by simulation itself, the benefits of formal verificati…
Verification
Featured Tutorial: Step-By-Step Guide to Advanced Verification Tutorial!, DVcon Exhibits and Product Demos.., DVCon Paper Presentations... etc.. more @ this link
Verification
This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing an organization’s clock-domain crossing verification skills, infrastructure, and metrics for measuring success while identifying process areas requiring improvement. This Clock-Domain Crossing Verification Module contains 7 sessions total including 1 demo.
Verification
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are available for Questa versions 6.2 to 6.4
VIP
Over the last decade functional verification of ASIC systems has witnessed a paradigm shift in verification methodologies. Until late 90's a verification project requirements were met by traditional test-benches written using a HDL(hardware description language, used for coding the design) or a software language like C. These test environments supported directed testing by generating a pre-calculated stream of input data only focusing on the…
Verification Plan
An effective verification plan encompasses a detailed description of the complete hierachical verification methodology at unit and full chip level. It is important to consider at what verification phase directed vs random tests will be applied or when to stop investing effort on building a stand alone test environment that can provide greater coverage and instead, migrate to full chip level tests that deliver a more comprehensive understanding o…
Verification
For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent pll model integration the whole scenario changed and i was in the middle of a clock jitter related timing check failure. This led me to do some Google search when i found this interesting 3 part article based on the same title. Defining clock jitter DDR2/DDR3 functionality Clock jitter and statistics
Verification
At a Glance, an ASIC (Application Specific Integrated Circuit) can consolidate the work of many chips into a single, smaller, faster package reducing the manufacturing and support costs while boosting the speed of the device built with this technology. ASIC technology is so advanced that many functions traditionally implemented in software can be migrated into ASIC's functionality. More specifically, ASIC let designers think in terms of Har…
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shivayogi
March 02, 2009
Verification
ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon) by Richard Munden "As large and complex as today's FPGAs are, they always end up on a board..." ( more ) Key Phrases: path delay section , negative timing constraints , skew violation , Free Model Foundry , Output Glitch Detection Variables , Vital Memo ( more... ) Review Today it is still very difficult to verify board …
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The Editor's Desk
December 04, 2007
