The Digital Electronics Blog

Bangalore

Intel Mobile Comm's is looking for a Senior Verif Engineer

Murugavel -2:41 PM BBC 1

Code Reviews

Peer code review of RTL, Test bench, Test Cases for 100% Verification closure

mg -5:15 PM BBC 1

cadence

Acceleration And Emulation – Why HW/SW Integration Needs Both

mg -2:27 PM BBC 1

cadence

Cadence Debuts Verification Computing Platform

Murugavel -5:10 PM BBC 1

DRAM

SDRAM Memory Systems: Architecture Overview and Design Verification

mg -2:37 PM BBC 1

AVM

Enabling Rapid, Reliable Deployment of IP into System Designs

mg -7:14 AM BBC 1

Flow

Evolving the Coverage-Driven Verification FlowEvolving the Coverage-Driven Verification Flow

mg -2:58 PM BBC 1

C++

Boosting RTL Verification with High-Level Synthesis

mg -8:24 PM BBC 1

CDC

Diagnosing clock domain crossing errors in FPGAs

mg -8:45 PM BBC 1

Debugging

The Art of Debugging: Make it Fail

mg -5:46 PM BBC 1

e-verification

e Verification language is alive and well

mg -8:33 PM BBC 1

Methodology

Toyota Prius 2005: An Early Warning About Verification

mg -5:50 PM BBC 1

Formal Verification

Motivation: What else can we talk about verification?

mg -3:10 PM BBC 1

DVCon

Verification Sessions at DVcon 2010

mg -9:53 PM BBC 1

CDC

Clock-Domain Crossing Verification Module

mg -7:15 PM BBC 1

Kits

Questa SV/AFV: Verification Methodology Kits

mg -2:38 PM BBC 1

HVL

The world of HVLs and VIPs

mg -4:19 PM BBC 1

Verification

Verification Plan

mg -7:32 PM BBC 1

DDR

Dealing with clock jitter in DDR2/DDR3 based designs

mg -3:52 PM BBC 1

Verification

SOC verification

shivayogi -10:26 PM BBC 1