Showing posts with label Glitch. Show all posts
Showing posts with label Glitch. Show all posts

Toyota's woes: More technology, more complexity

Today, cars can have as many as 70 electronic control units, or ECUs, based on microcontrollers (sometimes generically referred to as microprocessors). ECUs manage engines, doors, transmissions, seats, and entertainment, and climate systems. Electronic throttle systems use an array of sensors, microcontrollers, and electric motors to control how the car is accelerated. Gone are the old steel cables to connect the driver's foot to the engine. Because of all of this added complexity and the need for chips to talk to each other, a bus system was introduced--not unlike the Peripheral Component Interconnect, or PCI bus used in virtually all PCs today. Called the Controller-area network, or CAN-bus, it is designed to allow microcontrollers and devices to communicate with each other within a vehicle. Click the title for the main commentary!

Glitch in a combinational circuit and the way to avoid that.

A glitch resistive transition means, it is not possible to have any intermediate momentary values during output transition.

Consider the final logic gate in the below design, which is driving the output "O", "D" ns is propagation delay of the gate

d1 _____________
I1 -------| Final Logic |
|| Gate |--------- O
I2 -------|_____________|
logic & routing delay of I1 = d1
logic & routing delay of I2 = d2
Say d1 > d2; Skew d = d1-d2

Case 1:
No skew between the inputs I1 & I2 (d1 = d2)
* There will not be any GLITCHES at output.
* Output will be ready after D ns from an input change.

Case 2:
There is a skew "d" ns between the inputs I1 & I2 (the difference in logic and routing delay from the driving point cause the skew) (d1 != d2)
* Output will be settled after "d+D" ns from an input change.
* Outputs at "D to d+D" ns from an input change can have momentry unwanted vales (GLITCHES)

Solution 1
Keep the skew between the inputs as zero (no skew) for the output driving logic gate (Similar to Case 1).
Solution 2
Register the combinational output, so that the stable output can sample and hold it until an another stable output comes.
Register "O" with a sampling period "T" ns such that {d1 + D + Tsetup(of flip flop)} < T

Glitches, Hazards and Lizards

A glitch is a momentary error condition on the output of a circuit due to unequal path delays in a circuit. It is seen as an additional pulse or pulses on the output. Between a time the input signals are settled and the output signals are being established a glitch can occur if there is an hazard(functional or logical).

Glitches due to functional errors can occur when two input signals or more change in values at the same time. It is related to the function that is being implemented and cannot be removed by adding extra circuit.

Glitches due to logical hazard can occur only when one i/p signal changes it value. A logic hazard can be removed by add extra circuit. A logic hazard can be static or dynamic.