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A negative setup and hold condition is a very interesting proposition in static timing analysis. Support for this type of conditions was added in the Verilog LRM, only in the late 90's (using the $SETUP and $HOLD constructs). The basic idea is something like this: Consider a module with an ideal flop in it. Now, there exists a data path (from primary inputs of module to D of flop) and a clock path (from primary inputs to CLK of flop). Suppos…
a) Generally speaking SETUP fixing is always DIFFICULT. This can be resolved by inserting buffers (as you mentioned) only in cases where the SETUP violation is because of large load/slew violations which causes huge delays in combinatorial blocks. say there is an AND gate which is driving much more loads than it should and you see A to Y delay for that 3ns. Now this load violation can be fixed by adding a buffer after the AND gate and you may se…
The setup time is the time the data inputs must be valid before the clock/strobe signal. tSU(chip-pin)= tSU(FF) - Tdelay_clk_min(chip-pin to FF-pin) + Tdelay_data_max(chip-pin to FF-pin) The hold time is the time the data must remain valid after the clock/strobe signal. tH(FF) = clk2Q + Tcomb+T(clk-skew), where T(clk-skew) = clk diff b/w source and destination flops. If source sees clk at X and destination flop sees clk at Y, T(clk-skew) = Y-X t…