"Safe" and "Unsafe" state machines

"Safe" State Machines:
If the number of states (N) is a power of 2 and you use a binary or gray-code encoding algorithm, then the state machine is "safe." This ensures that you have M number of registers where N = 2M. Because all of the possible state values (or register statuses) are reachable, the design is "safe."

"Unsafe" State Machines:
If the number of states is not a power of 2, or if you do not use binary or gray-code encoding algorithm with fully defined states (e.g., one-hot), then the state machine is "unsafe" as it can stray into an undefined state.

FSM types and significance in detail:

Binary Encoding:
1. States are numbered starting from binary '0' and above.
2. '1' flip flop for very bit of the encoded binary number.
3. States are assigned in binary sequence.

Adv:
1. Lesser number of flip flops - log(n) for n states.
2. Less area, so good for area constrained circuits.

Dis-Adv:
1. More that '1' bit can flip anytime.
2. Getting into a stale state is possible.
3. Complex decoding logic is necessary to find the state that you are currently in.
4. More number of ff toggling at the same time causes more power to be consumed.

Gray Encoding:
1. States are numbered starting from binary '0' and above in gray style.
2. One flip flop for very bit of the encoded gray code.
3. Assign adjacent gray codes to adjacent states.

Adv:
1. Same number of ff's as binary.
2. Only '1' bit is different for adjacent states, so less chance of getting in to a stale state.
3. Only '1' ff changes at any given time so less power consumed.
4. Less area so good for area constarined circuits.

Dis-Adv:
1. Decoding logic is complex.


One Hot Encoding
1. Only '1' flip flop for every state rather than '1' flip flop for every bit..
2. Only '1' flip flop can be '1' at any time, all others must be '0'.

Adv:
1. Very simple decoding logic, so checking for a particular state is as easy as reading the correspoding ff.
2. '2' ff's change their state every time - less power.

Dis-Adv:
1. More ff's

Suited for FPGAs
1. Uses the ffs in the CLBs for state decoding.
2. Lesser number of routing hops required for decoding.