Free HDL Simulators for Verilog, SystemVerilog and VHDL

The best free HDL simulators today are Icarus Verilog and Verilator for Verilog and SystemVerilog, and GHDL and NVC for VHDL. All four are open source and actively maintained. If you need a mixed-language or full SystemVerilog simulator at no cost, the free editions that ship with FPGA vendor tools (AMD Vivado's built-in simulator and Questa Altera FPGA Starter Edition) and the browser-based EDA Playground are the practical options.

Free HDL simulators are a valuable resource for anyone working with hardware description languages, whether they are students, hobbyists or professionals. They let you experiment, learn new skills and develop digital designs without a significant financial investment. This post lists the main options, what each is good at, and where to download it, with every link checked in November 2026.

Key takeaways

• For learning Verilog, Icarus Verilog is the easiest start: one install, one command to compile, one to run.
• For fast simulation of large synthesizable designs, Verilator is the open-source standard, but it is two-state and needs a C++ compiler.
• For VHDL, use GHDL or NVC. Both support VHDL-2008, and NVC has the most complete VHDL-2019 support of the free tools.
• ModelSim Student Edition is currently unavailable from Siemens. Free ModelSim and Questa editions now come through FPGA vendors.
• Free commercial editions usually have limits: device-locked licences, slower performance or restricted features. Read the terms before you plan a project around one.

Why free simulators matter

Cost. Commercial HDL simulators are expensive. Free simulators let students, hobbyists and small companies with limited budgets learn and use HDLs without spending a lot of money.

Accessibility. Free tools remove financial barriers and help HDLs spread, in universities, in countries where commercial licences are hard to obtain and in open-hardware projects.

Community. Open-source simulators are developed by a community of developers and users. Their contributions bring more features, bug fixes and improvements that benefit everyone, and the source is there to read when you hit a strange behaviour.

Learning. Beginners can experiment with HDLs without any financial commitment. This is especially valuable for students and hobbyists exploring digital design and FPGA programming.

Automation. Open-source simulators have no licence server, so they run freely in continuous integration. Many teams run regression tests on every commit with Verilator or GHDL, even if they sign off with a commercial tool.

The free HDL simulators at a glance

Simulator	Languages	Type	Licence	Best for
Icarus Verilog	Verilog (IEEE 1364-2005), some SystemVerilog	Event-driven, four-state	Open source (GPL)	Learning Verilog, small designs and testbenches
Verilator	Synthesizable Verilog and SystemVerilog, growing testbench support	Compiles to C++, two-state	Open source (LGPL or Artistic)	Large designs, CPU cores, fast regressions, linting
GHDL	VHDL-87, -93, -2008 (partial 2019)	Compiled, event-driven	Open source (GPL)	VHDL learning and verification, VHDL synthesis via Yosys
NVC	VHDL-93 to VHDL-2019	Compiled, event-driven	Open source (GPL)	VHDL-2008 and 2019 features, fast compile
AMD Vivado simulator	VHDL, Verilog, SystemVerilog, mixed	Event-driven, four-state	Free entry-level tier	AMD FPGA projects, mixed-language designs
Questa Altera FPGA Starter Edition	VHDL, Verilog, SystemVerilog, mixed	Event-driven, four-state	Free, renewed yearly	Altera FPGA projects, ModelSim-style flow
EDA Playground	Depends on the simulator chosen	Browser front end to several simulators	Free account	Quick experiments, sharing examples, no install

Open-source simulators

Icarus Verilog

Icarus Verilog is a free and open-source Verilog simulator. It supports the Verilog-2005 standard, as well as some features of SystemVerilog (enable them with the -g2012 flag). It compiles your source to an intermediate file with iverilog and runs it with vvp. Simulation is four-state, so X and Z values behave as they would in a commercial simulator, which matters when you are learning how resets and uninitialised registers behave. Version 13.0 was released in March 2026, and Linux distributions, Homebrew and the Windows installers linked from the documentation all provide builds.

Icarus Verilog: https://steveicarus.github.io/iverilog/ (installation guide: https://steveicarus.github.io/iverilog/usage/installation.html)

Verilator

Verilator is a free and open-source Verilog and SystemVerilog simulator. Instead of interpreting the design, it converts synthesizable code into optimised C++ (or SystemC) and compiles that into an executable, which makes it one of the fastest simulators available, free or commercial, for large designs. Since version 5 it also handles delays, events and timing controls, so many testbenches that once needed a separate simulator now run in Verilator. It is widely used for processor cores and for linting, because its warnings catch many coding problems early.

Two points to know before you choose it. First, it is two-state: X values are converted to 0 or 1 (optionally at random), so it will not show X propagation the way a four-state simulator does. Second, it needs a C++ compiler and a build step, so it is less convenient for a first-time learner. Releases come out roughly monthly in the 5.x series.

Verilator: https://www.veripool.org/verilator/

GHDL

GHDL is a free and open-source VHDL simulator. It supports the VHDL-87, VHDL-93 and VHDL-2008 standards, with partial support for VHDL-2019. It compiles VHDL to machine code (using an LLVM, GCC or built-in code generator, depending on the build) and writes waveforms in VCD, FST or its own GHW format. Its synthesis front end also lets the Yosys open-source synthesis tool read VHDL. Version 6.0.0 was released in March 2026.

GHDL: https://github.com/ghdl/ghdl/releases (documentation: https://ghdl.github.io/ghdl/)

NVC

NVC is another open-source VHDL compiler and simulator, and the one with the most complete VHDL-2019 support of the free tools. It is fast to compile, runs common verification libraries such as OSVVM, UVVM and VUnit, and is actively developed, with release 1.23.1 published in October 2026. If GHDL fails on a VHDL-2019 feature, try NVC.

NVC: https://www.nickg.me.uk/nvc/ (source and releases: https://github.com/nickg/nvc)

Free editions of commercial simulators

ModelSim Student Edition (currently unavailable)

ModelSim Student Edition was a free, limited version of the commercial ModelSim simulator from Mentor Graphics, now Siemens EDA. It supported VHDL and Verilog simulation and included a waveform viewer, and for years it was the default choice for university courses. When this post was checked in November 2026, the old Mentor link redirected to a Siemens page saying the student edition is temporarily unavailable because of changes in US federal regulations. Siemens suggests going through a university programme, or using the ModelSim and Questa editions that FPGA vendors bundle with their tools (below).

ModelSim Student Edition (status page): https://www.mentor.com/company/higher_ed/modelsim-student-edition

Questa Altera FPGA Starter Edition

Altera's Quartus Prime software includes a free Questa simulator edition, the Starter Edition. It supports VHDL, Verilog, SystemVerilog and mixed-language designs. The licence is free but must be requested each year through Altera's Self-Service Licensing Center and is tied to one computer. Altera states that the Starter Edition runs at a fraction of the full edition's speed, which is fine for coursework and small FPGA designs. It is the closest free equivalent to the old ModelSim Student Edition.

Questa Altera FPGA editions: https://www.altera.com/downloads/fpga-development-tools/questa-altera-fpga-and-starter-editions

AMD Vivado (formerly Xilinx Vivado WebPACK)

Xilinx Vivado WebPACK was the free version of Vivado from Xilinx, which is now part of AMD. Its built-in simulator (xsim) supports VHDL, Verilog, SystemVerilog and mixed-language simulation and includes a waveform viewer. The free edition was later renamed Vivado ML Standard Edition, and from the 2026.1 release AMD moved Vivado to a tiered licensing model that still includes a free entry-level tier. The free tier covers smaller devices only, so check that your target FPGA is included. The simulator itself works without any hardware.

AMD Vivado: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html (now redirects to https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html)

EDA Playground

EDA Playground is a free website where you write code in the browser and run it on a choice of simulators, including the open-source ones above and, after registration, some commercial ones. Nothing needs installing, and you can share a link to a working example, which makes it popular for interview preparation and for asking questions on forums. Its limits are run time and the fact that your code sits on someone else's server, so it is not for confidential work.

EDA Playground: https://www.edaplayground.com/

Worked example: your first Icarus Verilog run

The design and testbench below are a 4-bit counter with an enable. The testbench counts 18 clock edges, so the counter wraps past 15 and should read 2, then checks that it holds when the enable is removed. Save it as counter_tb.v.

`timescale 1ns/1ps
module counter #(parameter WIDTH = 4) (
  input  wire             clk,
  input  wire             rst_n,
  input  wire             en,
  output reg  [WIDTH-1:0] q
);
  always @(posedge clk or negedge rst_n)
    if (!rst_n)  q <= {WIDTH{1'b0}};
    else if (en) q <= q + 1'b1;
endmodule

module counter_tb;
  reg clk = 1'b0, rst_n = 1'b0, en = 1'b0;
  wire [3:0] q;
  integer errors = 0;

  counter #(.WIDTH(4)) dut (.clk(clk), .rst_n(rst_n), .en(en), .q(q));

  always #5 clk = ~clk;  // 100 MHz clock

  initial begin
    $dumpfile("counter.vcd");
    $dumpvars(0, counter_tb);
    #12 rst_n = 1'b1;
    @(negedge clk) en = 1'b1;
    repeat (18) @(negedge clk);
    if (q !== 4'd2) begin
      errors = errors + 1;
      $display("FAIL: expected q = 2 after wrap, got %0d", q);
    end
    en = 1'b0;
    repeat (3) @(negedge clk);
    if (q !== 4'd2) begin
      errors = errors + 1;
      $display("FAIL: counter moved while en = 0, q = %0d", q);
    end
    if (errors == 0) $display("PASS: counter wraps and holds correctly");
    $finish;
  end
endmodule

Compile and run it:

iverilog -g2005 -Wall -o sim counter_tb.v
vvp sim

The output should end with PASS: counter wraps and holds correctly. The run also writes counter.vcd, which you can open in a free waveform viewer such as GTKWave or Surfer to see the clock, reset and count. Note that the testbench drives inputs on the falling edge of the clock, half a cycle away from the active edge, which avoids races between the testbench and the design.

How to choose

• Learning Verilog: Icarus Verilog, plus GTKWave or Surfer for waveforms. Try EDA Playground if you cannot install software.
• Learning VHDL: GHDL or NVC.
• Large SystemVerilog RTL, fast regressions or a RISC-V core: Verilator, often driven by C++ or by the Python framework cocotb.
• UVM or full SystemVerilog testbenches: open-source support is still incomplete, so use a vendor edition or EDA Playground with a commercial simulator.
• Mixed VHDL and Verilog for an FPGA: the simulator that comes with your FPGA vendor's tools.

Common mistakes

• Expecting full SystemVerilog in Icarus Verilog. It supports a subset. Classes, constrained random and UVM will not work.
• Trusting a Verilator pass on X behaviour. Two-state simulation can hide reset and initialisation bugs. Check those in a four-state simulator too.
• Forgetting the licence renewal. Free vendor licences that expire after a year tend to stop working the week before a deadline.
• Driving testbench inputs on the active clock edge. This creates races whose result can differ between simulators.

Frequently asked questions

Is there a free SystemVerilog simulator that supports UVM?

Not fully among the open-source tools at the time of writing. Verilator's UVM support is improving, but for complete UVM flows most people use a vendor-bundled Questa edition or a commercial simulator through EDA Playground.

Which free simulator is fastest?

For large synthesizable designs, Verilator is usually much faster than event-driven simulators, because it compiles the design to optimised C++. For small designs, compile time dominates and the difference matters less.

Can I use these tools for commercial work?

The open-source simulators can generally be used commercially under their licences. Vendor free editions have their own terms, and EDA Playground's commercial simulators are licensed for evaluation and learning, so read each licence before using it on paid work.

Do I need an FPGA board to use a simulator?

No. Simulation runs entirely on your computer. A board is only needed when you want to program real hardware.