- Flip-flops are almost free in FPGAs, the reason is that in FPGAs, the area consumed by a design is usually determined by the amount ofcombinational circuitry, not by the number of flip-flops.
- Aim for using 80–90% of the cells on a chip, because if you use more than 90% of the cells on a chip, then the place-and-route program might not be able to route the wires to connect the cells. And if you use less than 80% of the cells, then there are optimizations that will increase performance and still allow the design to fit on the chip, or you spent too much human effort on optimizing for low area, or you could use a smaller (cheaper!) chip.
- Use just one clock signal because if all flip-flops use the same clock, then the clock does not impose any constraints on where the place-and-route tool puts flip-flops and gates. If different flip-flops used different clocks, then flip-flops that are near each other would probably be required to use the same clock.
- Use only one edge of the clock signal because there are two ways to use both rising and falling edges of a clock signal, they have rising-edge and falling-edge flip flops, or have two different clock signals that are inverses of each other. Most FPGAs have only rising-edge flip flops. Thus, using both edges of a clock signal is equivalent to having two different clock signals, which is deprecated by the preceding guideline.
General FPGA based design Guidelines
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Friday, January 06, 2006
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Based on past experience i had with FPGAs...
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