Basic aspects of a typical digital design flow...

• Requirements
• Description of what the customer wants
• Algorithm
• Functional description of computation. Probably not synthesizable. Could be a flowchart, software, diagram, mathematical equation, etc..
• High-Level Model
  
• HDL code that is not necessarily synthesizable, but divides algorithm into signals and clock cycles. Possibly mixes datapath and control. In VHDL, could be a singleprocess that captures the behaviour of the algorithm. Usually synthesizable; resulting hardware is usually big and slow compared to optimized RTL code.
• Dataflow Diagram
  
• A picture that depicts the datapath computation over time, clock-cycle by clock-cycle.
• Hardware Block Diagram
  
• A picture that depicts the structure of the datapath: the components and the connections between the components. (e.g., netlist or schematic)
• State Machine
  
• A picture that depicts the behaviour of the control circuitry over time.
• DP+Ctrl RTL code
  
• Synthesizable HDL code that separates the datapath and control into separate processes and assignments.
• Optimized RTL Code
  
• HDL code that has been written to meet design goals (high performance, low power, small, etc.)
• Implementation Code
  
• A collection of files that include all of the information needed to build the circuit: HDL program targeted for a particular implementation technology (e.g.a specificFPGA chip), constraint files, script files, etc.

Note: Recomendation Spend the time up front to plan a good design on paper. Use dataflow diagrams and state machines to predict performance and area. You will probably produce a more optimal design with less effort if you explore high-level optimizations with dataflow diagrams and state machines.