Gate Level Simulation, Part - II

Gate level simulation is used in the late design phase to increase the level of confidence about a design implementation and to complement verification results created by static methods (formal verification and static timing analysis). In addition to the disadvantages of medium to long run times to simulate comprehensive vector sets on large designs, the coverage of potential functional and timing problems highly depends on the quality of the input stimulus and cannot be guaranteed in a practical way. In some cases, however, a gate level simulation can help to verify dynamic circuit behavior that cannot be accurately verified with static methods. For e.g. the start up and reset phase of a chip. To reduce the overall cycle time, only a minimum amount of vectors should be simulated using the most accurate timing model available (parasitics extracted from post-layout database).

Unit Delay Simulation:
The netlist after synthesis, but before routing does not yet contain the clock tree. It does not make sense to use SDF backannotation at this step, but gatelevel simulation may be used to verify the reset circuit, the scan chain or to get data for power estimation. If no backannotation is used, simulators should use Libraries which have the specified block containing timing args disabled and using distributed delays instead. The default delay for a storage element at 10 ps, for a combinatorial gate 1 ps and a clock gating cell 0 is the most secure possibility to run unit delay simulation, and process size and performance are optimized if the specify block is disabled.

Full Timing Simulation (With SDF):
Simulation is run by taking full timing delays from sdf. The SDF file is used to back annotate values for propagation delays and timing checks to the Ver-ilog gate level netlist.

Comments are greatly appreciated.

Glossary of EDA Terms

http://www.eetimes.com/news/design/resources/edaterms.html

Verilog rules that can save your breath !

This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rules that will save you headaches if you follow, and how a Verilog file should be layed out.

Rules:

• If you don't know what hardware the code you just wrote is, neither will the synthesizer.
• Remember that Verilog is a Hardware Description Language (HDL) and as such it describes hardware not magical circuits that you can never actually build.
• You should be able to draw a schematic for everything that you can write Verilog for.
• Be sure to know what part of your circuit is combinational and which parts are sequential elements. If you do not know or the code is written to be too hard to figure this out, the synthesizer will probably not be able to figure it out either. I recomend making the combinational logic very separate from sequential logic. This prevents errors later. It also prevents level high latches from being synthesized where you meant to have flip-flops. I also recomend having a naming convention such that you can tell what is a state holding element at all times. I use "_f" post-pended to all registers that are flip-flops.
• I recomend having a style for your inputs and outputs. I list them in the following order: outputs, inouts, special inputs such as clk and reset, inputs.
• When instantiating a module, always put the names of the signals that you are conecting to inside of the module with the notations where you have period, module signal name, thing you are connecting. This prevents errors when you change underlying modules or someone resorts the parameters.
• Unlike a language like C which is rather strongly typed, in Verilog, which is also strongly typed, everyting is of the same type and it is easy to reorder parameters and not get errors becasue everything is just a wire.
• Example of wrong module instantiation: nand2 my_nand(C, A, B);
• Example of correct module intantiation: nand2 my_nand(.out(C), .in1(A), .in2(B));
• Make your circuit synchronous whenever possible. Synchronous design is much easier than asynchronous.
• Also reduce the number of clock domains and clock boundaries whenever possible.
• Also remember that crossing clock domains in FPGAs is difficult because LUT's glitch in different ways than normal circuits. This causes problems with asynchronous circuits.

Verilog files should be laid out like this..

• define consts
• declare outputs (these are _out)
• declare inouts if any (these are _inout)
• declare special inputs such as clk and reset
• declare inputs (these are _in)
• declare _all_ state (these are _f)
• declare inputs to state with (these have same name as state but are _temp)
• declare wires (naming not restricted except connections of two instantiated modules are usually of the form A_to_B_connection)
• declare 'wire regs' (naming not restricted except connections are usually of the form A_to_B_connection and variables that are going to be outputs, but still need to be read and you don't want inouts get _internal postpended)
• do assigns
• do assigns to outputs
• instantiations of other modules
• combinational logic always @'s are next
  do the always @ (posedge clk ...) and put reset values here and assign _temps to _f's (ie state <= next_state). I personally think that there should be no conbinational logic inside of always @(posedge clk's) with the exception of conditional assignment (write enables) becasue all Verilog synthesizers understand write enables on flip-flops.

VHDL Online

http://esd.cs.ucr.edu/labs/tutorial/VHDL_Page.html

• Books
• Tutorials
• Examples
• Tools
• Download
• Others

VHDL Tutorial: Learn by Example

• Basic Logic Gates
• Combinational Logic Design
• Typical Combinatinal Logic Components
  Latch and Flip-Flops
• Sequential Logic Design
• Typical Sequential Logic Components

http://esd.cs.ucr.edu/labs/tutorial/

Embedded System Design: A Unified Hardware/Software Introduction

Some web resources, references, labs, and slides.
http://esd.cs.ucr.edu/

VLSI Training Institutes

Updated 15 Jan 2011, by Guest Blogger:
Since this article was last published in Nov, 2006 lot of development has happened in the VLSI training space. To understand what is more suited for you and to select the right institution please read further at Career Counseling.
--
Responding to request from a reader "Venkat" regarding VLSI training institutes..

The first question i would ask anyone who is looking forward to joining a VLSI training institute is what exactly they are looking for? I will give links to some article where you can decide, later in the article.

I feel that many institutes teach just bare basics (which you can find on the blogs and websites around the net, or rather your 4 years of Engineering/BE/BS) after gulping huge lumpsums of $$. How many of these institutes target real problems? Or rather which will be helpful when you enter the industry and can say that i targeted so and so problem and solved it the so and so way. Wouldn't that be great. Atleast that you can say as experience.

Some teach assembly programming, verilog, VHDL etc. Which is ok, but can also be done by self learning with little effort. Why spoon feeding?

My answer to this query would be just plain "Dont go anywhere near them!" They are not worth it. Seriously !!

But if you still think that you need to throw away your money... then follow these links below..
http://www.angelfire.com/electronic/in/vlsi/training.html
http://in.geocities.com/srinivasan_v2001/technical/vlsi_training.html
http://www.asic-world.com/verilog/verifaq4.html