GLS
Gate Level Simulation, Part - II
Gate level simulation is used in the late design phase to increase the level of confidence about a design implementat…
Showing posts from November, 2006
Verilog
Verilog rules that can save your breath !
This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rul…
Embedded
Embedded System Design: A Unified Hardware/Software Introduction
Some web resources, references, labs, and slides. http://esd.cs.ucr.edu/