In digital logic design, there are different types of delay modeling. Some of the commonly used delay modeling techniques are:
Inertial Delay Model:
Inertial delay is a delay model that takes into account the input signal behavior for a certain amount of time before it changes the output. The output signal is not changed until the input signal remains stable for a certain period. It is also known as event delay or realistic delay.
Transport Delay Model:
Transport delay is a delay model that represents the time it takes for a signal to propagate through a wire or gate. In this delay model, the output signal changes after a certain amount of time that is equivalent to the propagation delay of the gate.
Delta Delay Model:
Delta delay is a zero-delay delay model that represents events that occur in the current simulation time. It is used to model instantaneous events.
Pure Delay Model:
Pure delay is a type of delay model that represents the fixed delay between two points in a circuit, without considering any input signals.
Here are some coding best practices to follow while modeling delays in digital logic:
Use delay modeling techniques that accurately reflect the behavior of the circuit being modeled. The choice of delay modeling technique depends on the type of circuit being modeled and the level of accuracy required.
Specify delays using explicit delay syntax, such as the "#" symbol in Verilog or the "after" keyword in VHDL, rather than using implicit delays.
Use comments to describe the purpose of the delay and any assumptions made in the delay modeling.
Use named constants or parameters to specify the delay values, rather than hard-coding the delay values in the code.
Make sure that the delay values used in the code are consistent with the delay values specified in the datasheet of the components used in the circuit.
Simulate the circuit with different input patterns to verify the accuracy of the delay modeling.
Use simulation tools that support different delay modeling techniques and can accurately simulate the circuit behavior.
By following these coding best practices, you can ensure that your digital logic designs are accurate and reliable.
Additional Verilog specific details:
- Do not place delays on the LHS/RHS of blocking assignments to model combinational logic.
- Do not place delays on the LHS of nonblocking assignments to model combinational logic.
- Place delays on the RHS of nonblocking assignments only when trying to model transport output-propagation behavior. This coding style will accurately model delay lines and combinational logic with pure transport delays; however, this coding style generally causes slower simulations.
- In general, do not place delays on the RHS of nonblocking assignments to model combinational logic. This coding style can be confusing and is not very simulation efficient. It is a common and sometimes useful practice to place delays on the RHS of nonblocking assignments to model clock-to-output behavior on sequential logic.
- Use continuous assignments with delays to model simple combinational logic. This coding style will accurately model combinational logic with inertial delays.Use always blocks with no delays to model complex combinational logic that are more easily rendered using Verilog behavioral constructs such as "case-casez-casex", "if-else", etc. The outputs from the no-delay always blocks can be driven into continuous assignments to apply behavioral delays to the models. This coding style will accurately model complex combinational logic with inertial delays.
- Placing delays on the LHS of blocking assignments in a testbench is reasonable since the delay is just being used to time-space sequential input stimulus events, but on RHS is not. Placing a delay on the RHS of any blocking assignment is both confusing and a poor coding style.
- Nonblocking assignments are less efficient to simulate than blocking assignments; therefore, in general, placing delays on the LHS of nonblocking assignments for either modeling or testbench generation is discouraged.
- This coding style is often used in testbenches when stimulus must be scheduled on future clock edges or after a set delay, while not blocking the assignment of subsequent stimulus events in the same procedural block.
- There are some multi-clock design verification suites that benefit from using multiple nonblocking assignments with RHS delays; however, this coding style can be confusing, therefore placing delays on the RHS of nonblocking assignments in testbenches is not generally recommended.
- Continuous assignments can be used anywhere in a testbench to drive stimulus values onto input ports and bi-directional ports of instantiated models.
Conclusions: Any delay added to statements inside of an block does not accurately model the behavior hardware and should not be done. The one exception carefully add delays to the right hand side of nonblocking assignments, which will accurately model transport delays, generally at the cost of simulator performance.
Adding delays to any sequence of continuous assignments, or modeling complex logic with no inside of an always block and driving the always outputs through continuous assignments with delays, accurately model inertial delays and are recommended coding styles for modeling combinational logic.
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