- Store each VHDL unit into a separate file except package header and body
- Signal assignments for renaming purposes should be avoided
- The names of clocks and resets should be unique in the whole design
- Soft macros: Data types at ports: std_(u)logic(_vector)
- Avoid custom data types (e.g., multidimensional arrays, records, enumeration types)
- Avoid gated clocks unless absolutely necessary
- Avoid latches unless absolutely necessary
- All outputs of synchronous modules should be registered
- Process only one clock in RTL-units
- Do not use the value of type’left for initializing of a signal or variable during reset
- Avoid unused ports, busses must be split accordingly
- Avoid homographs
- Do not define a subprogram for a subtype only
- Comment each process, each subprogram and global aspects
- Processes should be labeled
- Aliases are not recommended
- Bussed ports of width one are forbidden
- Use case-statements instead of if-statements when the conditions are mutually exclusive
- All signals and variables should be read at least once
- Static ports should not exist
- Use a separate library clause for each declared resource library
- Use a separate use clause for each declared package
- Maximum line-length is 100 characters
- Order of ports in entity, component and instance should be the same
- Do not have unused signals
- Minimize the number of signals of your sensitivity list
- Avoid unnecessary computations within loops
- Use sensitivity lists instead of wait statements
- Subprograms may not have any side effects
HDL Coding Guidelines - Part 6
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January 20, 2008
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To Avoid common Warnings
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