- Balance clock to delta accuracy
- Pull-ups and pull-downs have to be modeled on chip level
- Communication between modules using text-IO is forbidden
- No characters with a lower rank than space may occur in text-IO
- Testbench and DUT should be compiled into the same library
- Asynchronous parts should be placed into separate entities
- VHDL units should take into account later floorplanning
- A FSM must be described in a separate entity/architecture pair
- Only verified VHDL code allowed for check-in
- Identifier naming must be based on English language
- Use meaningful identifier names
- Separate identifier components using underscores
- Instantiate the power pads for each power domain
- Gate instantiation must be encapsulated by separate unit
- Spend extensive efforts for documentation of interfaces
- Request external VHDL code suppliers to deliver used arithmetic packages
- Spacer cells needed between pads
- Signals that cross clock domains must be synchronized by synchronization cells
- Language for comments and code documentation is English
- Comments should be related to the lines of code below
HDL Coding Guidelines - Part 5
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January 20, 2008
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Critical Policies to Keep note!
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