NVIDIA Interview Question

Circuit below, which implements operation C, has been designed such that it has two modules i and j, with the delays shown in the given figure below. The latency for circuit b is 2 and the delay through a register is 5ns. Assume that circuits a and b are stages of a pipeline as shown in the figure below.
















NOTES:
1. The pipeline has 2 stages where the first stage of the pipeline contains circuit a (executing operation A or B) and the second stage of the pipeline contains circuit b (executing operation C).
2. Stage 2 reads the output of stage 1 as soon as it is available even if the two operations of stage 1 (i.e. A and B) have imbalanced latencies.
3. The pipeline has registers only on the inputs of the stages
4. The performance and cost overhead due to control circuitry (e.g. Mux) is not considered in this preliminary analysis.

Based on your analysis in the earlier post, what is the total time required to execute 100 input parcels sent through the pipeline?