NVIDIA Interview Questions: 9 True or False Statements Answered

This NVIDIA interview question set is a rapid true-or-false round: nine statements on RTL simulation, resets, FPGA lookup tables, memory dependencies, high-level models, hold fixes, voltage scaling, Gray-coded state machines and redundant faults. Seven of the nine are false and two are true, and every one needs a justification, which is what the interviewer is really grading. Each statement below is kept as posted and followed by the answer and the reasoning.

Key takeaways

• Answers: 1 True, 2 False, 3 False, 4 False, 5 False, 6 True, 7 False, 8 False, 9 False.
• Words like "all", "only", "without affecting" and "requires a minimum of" usually signal a false statement; find the counterexample.
• Justify with a mechanism (why it is true) or a concrete counterexample (why it is false).
• The round touches simulation, RTL design, FPGA mapping, timing, power and test: a quick check of breadth across the flow.

The question

State whether each of the following statements is True or False. Justify your answers.

1. RTL simulation is faster than delta-cycle simulation but can not be used in all situations.
2. When doing RTL design, all flip-flops need to have a reset input that is synchronized with the clock.
3. If P is a 16-bit unsigned signal, testing if P = 656 requires a minimum of 16 FPGA cells each having an LUT with 4 inputs, 1 output, a carry-in, and a carry-out.
4. Because there are two types of memory operations (Read and Write), there are four different types of data dependencies that can exist between memory operations.
5. When doing RTL design, a HLM can be written only after input/output allocation is done.
6. If the hold time of a flip-flop is violated, a possible solution would be to add buffers at the input of that flop.
7. Voltage scaling is a power reduction technique that relies on reducing the supply voltage of a circuit without affecting any of the other circuit parameters.
8. Because of the small number of transitions between codes, a 32-state finite state machine that uses Gray coding will consume less power than one that uses binary coding.
9. If a circuit contains some redundant components, all faults in the redundant circuitry are undetectable.

Answers with justification

1. RTL simulation vs delta-cycle simulation: True

RTL (cycle-based) simulation evaluates each register once per clock cycle and the combinational logic between registers in dependency order, so it does far less work than event-driven simulation. Delta-cycle simulation follows the full language semantics: every signal change schedules new events, and zero-delay updates are ordered in delta cycles. The speed comes at a cost: cycle-based simulation needs a fully synchronous design with no combinational loops, latches or asynchronous behaviour, and it cannot show glitches or event-ordering effects. So it is faster but not usable everywhere. For background on delta cycles, see transport, inertial and delta delay in VHDL and Verilog.

2. Every flip-flop needs a synchronous reset: False

Two parts are wrong. First, not every flop needs a reset: control state (FSM state, valid bits, counters) must be reset, but datapath registers whose contents are qualified by a valid bit often have no reset, which saves area and routing. Second, the reset need not be synchronous: asynchronous reset is common, as long as its de-assertion is synchronised to the clock.

module reset_mix (
  input  wire       clk,
  input  wire       rst,
  input  wire       in_valid,
  input  wire [7:0] in_data,
  output reg        out_valid,
  output reg  [7:0] out_data
);
  // control: must be reset
  always @(posedge clk)
    if (rst) out_valid <= 1'b0;
    else     out_valid <= in_valid;

  // data: no reset needed, qualified by out_valid
  always @(posedge clk)
    if (in_valid) out_data <= in_data;
endmodule

3. 16 LUT cells to test P = 656: False

An equality test against a constant must look at all 16 bits, but each 4-input LUT can compare 4 bits with the matching 4 bits of the constant at once. Four LUTs produce four partial-match signals. These are combined either with one more LUT (5 cells) or by chaining them through the carry logic (4 cells, if the carry chain can perform the AND). The minimum is therefore 4 or 5 cells, not 16. The value 656 (binary 0000 0010 1001 0000) makes no difference; any 16-bit constant needs the same.

module eq656 (input wire [15:0] p, output wire hit);
  assign hit = (p == 16'd656);
endmodule

4. Four types of data dependency: False

Two operations taken in pairs give four orderings: read after write (RAW), write after read (WAR), write after write (WAW) and read after read (RAR). Only the first three constrain the order of operations. RAW is a true dependency; WAR and WAW are name (false) dependencies that still must be respected or removed by renaming. Two reads can be reordered freely, so RAR is not a data dependency in the sense that matters for scheduling. There are three, not four.

5. A high-level model only after I/O allocation: False

A high-level model (HLM) captures what the design computes, at the algorithm level, and is normally written first: it becomes the reference against which the RTL is checked. Input/output allocation (which port carries which value in which clock cycle) is a later implementation decision. Only a cycle-accurate model of the interface depends on it, not the high-level model itself.

6. Add buffers to fix a hold violation: True

A hold violation means new data reaches the flop too soon after the clock edge. Adding buffers or delay cells in the data path, close to the flop's D input, increases the minimum path delay until the hold requirement is met. Two cautions belong in a full answer: the added delay must not create a setup violation on the same path, and the buffers must go on the data path, not the clock path, because delaying the capture clock makes hold worse. See setup time and hold time explained.

7. Voltage scaling with nothing else affected: False

Dynamic power is proportional to C x V² x f, so lowering the supply voltage saves power quadratically. But gate delay rises as the supply approaches the threshold voltage, so the maximum clock frequency falls; noise margins shrink; and the circuit may need level shifters where it meets other voltage domains. Voltage scaling works precisely because designers accept a lower frequency (or add parallel hardware) in exchange for power.

8. Gray-coded 32-state FSM always uses less power: False

Gray coding guarantees a single bit change only between neighbours in the Gray sequence. That suits counters and machines that mostly step through states in order. A general 32-state machine has transitions between arbitrary states, where a Gray code can flip several bits just like binary. The state register is only 5 flops in either case; most power is in the next-state and output logic, which the encoding can make larger or smaller. Power depends on the actual transition probabilities, so the statement is not true in general.

9. All faults in redundant circuitry are undetectable: False

A redundant component causes at least one undetectable fault, but not every fault in it is undetectable. Example: f = ab + a'c + bc, where bc is the redundant consensus term.

• bc output stuck-at-0: f is unchanged for every input, so the fault is undetectable.
• bc output stuck-at-1: f becomes 1 always. Apply a = 1, b = 0 (c either value): the good circuit gives 0, the faulty one gives 1, so the fault is detectable.

module consensus (input wire a, b, c, output wire f);
  assign f = (a & b) | (~a & c) | (b & c);  // b&c is redundant
endmodule

This is why test engineers remove redundancy where possible: undetectable faults lower fault coverage and can mask other faults. A short definition of design for test is in the Semiconductor Hub glossary entry on DFT (design for test).

Summary table

No.	Topic	Answer	One-line reason
1	RTL vs delta-cycle simulation	True	Faster, but needs fully synchronous logic with no loops or latches
2	Resets on all flops	False	Datapath flops often need none; async reset is allowed
3	16 LUTs for P = 656	False	4 or 5 cells
4	Four dependency types	False	RAW, WAR, WAW; RAR does not constrain order
5	HLM after I/O allocation	False	HLM comes first; I/O allocation is later
6	Buffers fix hold	True	More data path delay, check setup
7	Voltage scaling has no side effects	False	Delay rises, frequency must drop
8	Gray FSM uses less power	False	Only for mostly sequential transitions
9	Redundant faults all undetectable	False	Consensus term stuck-at-1 is detectable

How interviewers extend this question

• "Rewrite statement 7 so it becomes true." For example: voltage scaling reduces power by lowering the supply, at the cost of a lower maximum frequency.
• "Which encoding would you pick for a 32-state FSM on an FPGA, and why?" One-hot is a common answer on FPGAs because flops are plentiful and next-state logic stays shallow.
• "Can a hold violation be fixed by slowing the clock?" No: hold does not depend on the clock period.
• "How do you find redundant logic?" Automatic test pattern generation reports faults it proves untestable.

Related NVIDIA interview questions

This post is one of five posted on the same day:

• NVIDIA clock period question for two operations with different delays
• NVIDIA pipeline question: total time for 100 input parcels
• NVIDIA power reduction question for a two-stage image pipeline
• NVIDIA power question extended to a branching four-stage pipeline

Frequently asked questions

What kind of questions does NVIDIA ask in hardware interviews?

This set, posted as NVIDIA interview questions, covers simulation, RTL design, FPGA mapping, timing, low power and test, with an emphasis on justifying each answer.

How should I answer true-or-false hardware questions?

Give the verdict first, then one mechanism or one counterexample. A counterexample is the fastest way to prove a statement false.

Why is read after read not a data dependency?

Two reads of the same location return the same value in either order, so the order does not need to be preserved.

Does every redundant circuit have an undetectable fault?

Yes. That is the definition of redundancy used in test: a line is redundant if a stuck-at fault on it cannot change any output. Other faults in the same logic may still be detectable.