Justify your answers.
- RTL simulation is faster than delta-cycle simulation but can not be used in all situations.
- When doing RTL design, all flip-flops need to have a reset input that is synchronized with the clock.
- If P is a 16-bit unsigned signal, testing if P = 656 requires a minimum of 16 FPGA cells each having an LUT with 4 inputs, 1 output, a carry-in, and a carry-out.
- Because there are two types of memory operations (Read and Write), there are four different types of data dependencies that can exist between memory operations.
- When doing RTL design, a HLM can be written only after input/output allocation is done.
- If the hold time of a flip-flop is violated, a possible solution would be to add buffers at the input of that flop.
- Voltage scaling is a power reduction technique that relies on reducing the supply voltage of a circuit without affecting any of the other circuit parameters.
- Because of the small number of transitions between codes, a 32-state finite state machine that uses Gray coding will consume less power than one that uses binary coding.
- If a circuit contains some redundant components, all faults in the redundant circuitry are
undetectable.