Justify your answers.

- RTL simulation is faster than delta-cycle simulation but can not be used in all situations.
- When doing RTL design, all flip-flops need to have a reset input that is synchronized with the clock.
- If P is a 16-bit unsigned signal, testing if P = 656 requires a minimum of 16 FPGA cells each having an LUT with 4 inputs, 1 output, a carry-in, and a carry-out.
- Because there are two types of memory operations (Read and Write), there are four different types of data dependencies that can exist between memory operations.
- When doing RTL design, a HLM can be written only after input/output allocation is done.
- If the hold time of a flip-flop is violated, a possible solution would be to add buffers at the input of that flop.
- Voltage scaling is a power reduction technique that relies on reducing the supply voltage of a circuit without affecting any of the other circuit parameters.
- Because of the small number of transitions between codes, a 32-state finite state machine that uses Gray coding will consume less power than one that uses binary coding.
- If a circuit contains some redundant components, all faults in the redundant circuitry are

undetectable.

Hi,

ReplyDeletePlease can you post the answers to the questions in detail.

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I am not sure about all the answers but trying to answer some of them. Please verify somewhere else too.

ReplyDelete2) No. Asynchronous resets are used in the designs too. However synchronous reset is normally adopted.

6) Yes. Before the chip has been taped out, if there is a hold violation, the addition of buffers should resolve them.

7) Voltage scaling is scaling down the supply voltages with an intention of reducing the power dissipation. Other parameters do get affected by it. For eg: Threshold voltage and delay.

9) Well, it is not necessarily true. the redundant logic can also be tested for faults.

3) this is justification for statement 3:

ReplyDeleteto check if a 16 bit number is some constant requires a 16 input AND gate.

theoretically, if one views "P=656" as selecting one entry in the truth table formed all combinations (2^16) input P, then P=656 => P9&P7&P4&(all other bit positions zero). this follows from the binary representation of 656. a 16 input AND can be created with 4 LUTs for 1st stage compression and one more LUT for final compression. So, 5 LUTs are required

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8) Yes, basic concept is true. You will find that for an N-bit binary counter, For the 1st bit, N bits toggle, then for the 2nd bit, N/2 bits toggle, then for the 3rd bit, N/4 bits toggle. So calculating the total number of toggles (switches), we see a total of N+N/2+N/4+N/8+... toggles, which converges to 2*N toggles for a normal binary counter. For a gray counter, for N bits, since every count we only change 1 bit, we have N toggles total for each min to max count. So for a 32-bit state, which translates to 5 bits, we can have 50% lower power consumption in dynamic switching power from just using a gray counter. HOWEVER, one must remember that at very low power levels, leakage power becomes exponential - so there's a level of whether you really care that much about implementing gray coding using up valuable real estate space on your chip layout to do this.

ReplyDelete9) False. Redundancy in a sub-circuit means that there exists an undetectable fault (ex: stuck-at faults) in that sub-circuit. This does not mean it masks ALL of the other faults!

ReplyDelete