### custom_date('18 March 2009'); Interview Question

It has been a while since we posted any puzzles or interview questions to tickle everyone's teeny brains. Recession has hit us in a big way and there seems to be a running drought in originality of the interview questions asked now-a-days. Even the ones shared on the various blogs that have cropped up these days are either ruthlessly copied or "massaged". Dont you think so? So to say, that while keeping the spirit or creativity and intelligence alive and hoping that the recession passes without much a casualty here is one next in line to our trend of Original Interview Questions. Hurray!

Look at the following block. This is the most common building in any FPGA. It is called a Logic Element(LE) by Altera and Configurable Logic Element(CLB) by Xilinx. The structure may not be accurate but illustrates the idea behind it.

We estimate the number of FPGA cells required for a design by counting the number of flip-flops and primary inputs that are in the fanin of each flip-flop. Only flip-flops count, because combinational signals are collapsed into the circuity within an FPGA cell. The circuitry for any flip-flop signal with up to four source flip-flops can be implemented on a single FPGA cell. If a flip-flop signal is dependent upon five source flip-flops, then two FPGA cells are required.

This technique is generally an overestimate, because a single cell can drive several other cells (common sub expression elimination).

Coming to the Question...

Map the combinational circuits below onto generic FPGA cells. You could explain in words on how you could achieve this or send me an email. Appreciate your comments. Based on the solution received, i will post the answers here later! Good luck!

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OutputLogic said on October 24, 2009 at 11:59 AM

Correction: Xilinx CLB is Configurable Logic Block. The drawing is representing not CLB but a Slice.