Happy New Year 2010

Wishing all our readers a very happy new year 2010!

The world of HVLs and VIPs

Over the last decade functional verification of ASIC systems has witnessed a paradigm shift in verification methodologies. Until late 90's a verification project requirements were met by traditional test-benches written using a HDL(hardware description language, used for coding the design) or a software language like C. These test environments supported directed testing by generating a pre-calculated stream of input data only focusing on the desired coverage points in the design.As the design size and complexity grew exponentially, with a million gate design becoming the norm, clearly the directed verification approach is quite cumbersome. It is an almost impossible task to manually code the test vectors to test your million gate design under all operating conditions. The ever increasing aggressive project schedules also pushed in favor of a powerful yet easy to develop test environment. Hardware verification langauages (HVL) came as a boon to solve all these problems. HVLs typically include features of high level programming languages like C++ or Java and in addition they support built-in constructs which help you develop the environment with fewer lines of code. It is much easier to generate random stimuli or constrained random stimuli, as needed and the built in HDL interface support let’s you hook up the environment and the DUT seamlessly.

Of the handful of HVL choices available in the market SystemVerilog and e language (Specman) are the most popular and widely adopted by semiconductor companies. The reason for these two languages being the preferred choice is not just the language features itself but the accompanying methodology prescribed by the EDA vendors (ex: OVM/VMM for SV and eRM for e language). These methodologies provide guidelines to build modular, re-usable and extensible verification modules which support plug and play development. With most of the silicon designs today adopting the SoC (System-on-Chip) methodology where several design IPs are integrated on a single chip, there is a new requirement for corresponding verification IPs (VIP). By taking advantage of the VIPs available in market, the verification team can build a test environment for a complex SoC with minimal resource and time utilization. A standard verification methodology serves as a common platform for the various third party VIP developers and its customers. So it’s actually the verification methodology rather than the language which influences the decision on VIP selection. Some methodologies have made it possible to integrate verification modules written in different languages so that you don’t have to discard any legacy code if available (you may have to make it methodology compliant though). VIPs and verification methodologies are still relatively newer concepts to the verification world and is being tried out in experimental phases by semiconductor companies. Not all of the industry leaders have adopted these methodologies completely probably because of the overhead in training their current workforce and replacing the legacy code. Here’s hoping that the EDA vendors enhance their methodologies to make it more developer friendly.

Verification Plan

An effective verification plan encompasses a detailed description of the complete hierachical verification methodology at unit and full chip level. It is important to consider at what verification phase directed vs random tests will be applied or when to stop investing effort on building a stand alone test environment that can provide greater coverage and instead, migrate to full chip level tests that deliver a more comprehensive understanding of the sate of the chip.

A good verification plan addresses many questions like what tools can be used for stand alone and full chip and for what specific type of tests. Creation of expected result scenarios along with the self checking mechanism should be detailed to improve automation and to drive the highest return on performance. In addition to each verification phase, testbench deliverables, dependencies like RTL availability, milestones like tests to be completed or written and any assumptions need to be specified and understood thoroughly. Finally, upon completion of the verification plan it has to be reviewed by both the design and verification teams and a matrix has to be created to track test coverage and then use it to measure the completeness or progress. Is is also important to know when and how to apply technologies such as emulation and formal methods to leverage key strengths to avoid any weaknesses and achieve high design quality using the verfication effort.
Courtesy: Catherine Ahlshlager!

Single-atom transistor discovered

Researchers from Helsinki University of Technology (Finland), University of New South Wales (Australia), and University of Melbourne (Australia) have succeeded in building a working transistor, whose active region composes only of a single phosphorus atom in silicon. The results have just been published in Nano Letters.

The working principles of the device are based on sequential tunneling of single electrons between the phosphorus atom and the source and drain leads of the transistor. The tunneling can be suppressed or allowed by controlling the voltage on a nearby metal electrode with a width of a few tens of nanometers.

Original research article has been published in Nano Letters on Dec. 1st, 2009:
Transport Spectroscopy of Single Phosphorus Donors in a Silicon Nanoscale Transistor,
Kuan Yen Tan, Kok Wai Chan, Mikko Möttönen, Andrea Morello, Changyi Yang, Jessica van Donkelaar, Andrew Alves, Juha-Matti Pirkkalainen, David N. Jamieson, Robert G. Clark, and Andrew S. Dzurak,
Nano Lett., Article ASAP, DOI: 10.1021/nl901635j (2009).

For more information, please contact:

Dr. Mikko Möttönen, Helsinki University of Technology, Department of Applied Physics, firstname.surname@tkk.fi, tel. +358 9 470 22342 or +358 50 594 0950

Prof. Andrew Dzurak, University of New South Wales, Centre for Quantum Computer Technology, a.dzurak [at] unsw.edu.au, tel. +61293856311

Nokia Developer Conference, Bangalore, 7th Dec 2009

We have got a special invite to the Forum Nokia Developer Conference on 7th Dec 09 @ Bangalore. Please follow the complete coverage here at this blog. More info

Dealing with clock jitter in DDR2/DDR3 based designs

For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent pll model integration the whole scenario changed and i was in the middle of a clock jitter related timing check failure. This led me to do some Google search when i found this interesting 3 part article based on the same title.

Defining clock jitter
DDR2/DDR3 functionality
Clock jitter and statistics

Job openings @ Infineon India

Please see attached flier for more details...

Importance of soft skills

The semiconductor industry in general demands two special skills in every engineer. One of these skills is more trivial, that being the technical know-how and ability to grasp requirements & specifications. The other one is soft skills. The first one is mainly used to perform the required verification duties at work, and second one helps in planning an approach to solve the impending issues or problems. The bottom line is that a good engineer will have a blend of both technical and soft skills.

Technical skills are more profound in people with greater hands on experience. Needless to say, the more adventurous you are to dive deep and the more complex your targets are, the more you learn and this is where you really add value. Technical skills will eventually teach you how to meet these expectations.

Soft skills are the ones that define an engineer’s approach towards work and life and in most cases define stress that is more individual specific. Soft skills are actually people or inter-personnel skills. The best part about mastering it is that the application of these skills is not limited to one's profession, but their scope reaches beyond. Soft skills teach one to succeed, and to exceed expectations. There are situations that we come across during our day-to-day work life as a design or verification engineer in which one person performs better than the others just on the basis of Soft skills - be it winning an argument with someone on the basis of his/her communication or finding/handling multiple tasks effectively because of superior organizational abilities.

Soft skills are extremely important for engineers and this is something that is often overlooked. It is surprising that we spend most of our time educating almost exclusively in technical skills while thinking you are good at soft skills.

Our reactions in a complex setting vary widely with situations, emotions, requirements, time, belief, knowledge and expertise. Being such complex, a normal human being will be no exception at a work place where the stakes are very high. Therefore the quality of a job done by an engineer is directly proportional to his or her psychological maturity and profoundness acquired, adopted and developed with age and experience. be able to learn them.