VN-Cover seamlessly works with all leading simulators to measure coverage on VHDL, Verilog, SystemVerilog and mixed-language designs. It is a vendor-neutral coverage tool that works across simulators, languages and platforms, and can be also utilized with hardware-accelerated verification environments.
Key Features:
* Verilog, VHDL and mixed-language support
* Detailed code coverage reports and graphical display
* Automatic FSM extraction and analysis
* Advanced and unique glitch filtering capability
* Post-simulation coverability analysis option and results filtering
* Test-suite optimization facility
* Multi-platform, multi-simulator availability
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