Silicon characterization testing is the detailed measurement of a new chip's electrical and performance behaviour across voltage, temperature and process variation, done on a sample of real parts before the product is released. Its aim is to find out how the silicon actually behaves and where its limits are, so that the datasheet specifications, the production test limits and any design fixes are based on measured data rather than simulation alone. It is different from production test, which checks every unit quickly against limits that characterization has already set.
Image courtesy: MPI corp
Key takeaways
- Characterization measures electrical parameters such as voltage, current, capacitance, timing and frequency over a range of operating conditions, not just at one nominal point.
- It is run on a statistically chosen sample of parts, often including deliberately skewed process corners, not on every unit.
- Its outputs are the datasheet minimum, typical and maximum values, the guard-banded production test limits and feedback to the design team.
- It happens at wafer level on test structures and early dies, and on packaged parts on the bench and on automatic test equipment (ATE).
- Shmoo plots and parameter distributions are the two most common ways the results are shown.
What characterization testing measures
Characterization testing is a type of testing performed on silicon chips and integrated circuits to determine their electrical and performance characteristics. During characterization, devices are put through a series of tests that measure electrical parameters such as voltage, current and capacitance, along with timing and functional behaviour. The results form a "characterization" of the device: its safe operating conditions, its performance specifications and its electrical parameters, each with a measured spread.
The parameters depend on the type of chip, but a typical list looks like this:
| Area | Typical parameters | Why it matters |
|---|---|---|
| DC | Supply current (active and standby), leakage, input and output voltage levels, pin leakage, ESD and latch-up | Power budget, interface compatibility, robustness |
| AC and timing | Maximum frequency, setup and hold times, propagation delays, output rise and fall times | Speed grade and interface timing in the datasheet |
| Functional margins | Minimum operating voltage (Vmin), memory read and write margins, PLL lock range | Where the part stops working and how much margin is left |
| Analog and mixed-signal | Offset, gain, linearity (INL and DNL), noise, ADC SNR and ENOB, regulator accuracy | Performance figures customers design to |
| High-speed I/O | Eye height and width, jitter, return loss, bit error rate | Compliance with interface standards |
| Device level (wafer test structures) | Transistor threshold voltage, drive current, capacitance, resistance of contacts and vias | Process monitoring and model correlation |
Why it matters
Characterization testing is an important step in the development of silicon chips and integrated circuits. It confirms that the design behaves as intended across its full operating range and that it can meet the required specifications with margin. The information is used to optimise the design, to improve its performance and to find issues that could affect yield or reliability.
Simulation uses models, and models are never perfect. Characterization closes that gap in three ways:
- Datasheet values. The minimum, typical and maximum figures a customer reads come from measured distributions across many parts and conditions.
- Production test limits. Production test has to be fast, so it tests a subset of parameters at a few conditions. Characterization shows which tests are needed, at which conditions, and how much guard band to apply.
- Design and model feedback. Differences between measured and simulated behaviour point to design weaknesses, layout effects or model errors. These feed a metal fix, a new stepping or updated models for the next design.
When it is done
Characterization starts as soon as first silicon is available and continues until the product is qualified for volume. Some of it happens early, at wafer level, before devices are packaged: probe stations such as the one in the image above measure transistors and test structures on the wafer, and wafer sort data on early lots gives a first look at the spread. This catches problems early, when fixing them costs least. Most product-level characterization, however, is done on packaged parts on bench set-ups and on ATE, because package parasitics, thermal behaviour and the final pin interface all affect the results.
Characterization is also done on new and novel designs to validate the design and to provide a baseline for comparison with future designs. It is repeated in smaller form after a process change, a die shrink, a new package or a new assembly site.
How it is done
Choosing the sample
Parts are chosen to cover the expected process spread. Fabs can run corner lots (also called skew lots), where wafers are deliberately processed towards fast and slow transistor corners, for example fast-NMOS fast-PMOS (FF), slow-slow (SS) and the cross corners FS and SF. Testing those together with typical (TT) parts shows how the product behaves at the edges of the process window, not just in the middle.
Sweeping the conditions
Each part is tested across supply voltage and temperature. A common set is the minimum, nominal and maximum supply, often with extra margin beyond the specified range, at cold, room and hot temperature. The temperature range follows the product grade, for example 0 to 70 C for many commercial parts, -40 to 85 C for industrial and up to 125 C or 150 C for automotive grades defined under AEC-Q100. Thermal forcing systems or temperature chambers hold the part at each temperature.
Shmoo plots
A shmoo plot is a grid of pass and fail results as two conditions are swept, most often supply voltage against frequency. It shows at a glance where the part works, where it fails and whether the boundary has the expected shape. A wall that bends the wrong way, or holes in the passing region, often points to a specific circuit problem.
Illustrative example. Suppose a block is specified at 1.0 GHz from 0.72 V to 0.88 V. Characterization on 30 slow-corner parts at 125 C shows the worst part passes 1.0 GHz down to 0.70 V. That leaves only 20 mV of margin at the bottom of the range for the slowest silicon, at the hottest condition. The team might respond by setting the production Vmin test at 0.74 V to cover tester accuracy and ageing, or by asking design to look at the slowest path before volume. These numbers are illustrative, not from a real product.
Distributions and statistics
For each parameter the results across parts are plotted as a distribution. Engineers look at the mean, the standard deviation and the process capability index (Cpk), which compares the distance from the mean to the nearest specification limit with three standard deviations. A Cpk of 1.33 or more is a common target for a stable parameter.
Illustrative example. A regulator output has a specification of 1.200 V plus or minus 30 mV. Measured parts have a mean of 1.205 V and a standard deviation of 6 mV. The nearest limit is 1.230 V, 25 mV from the mean, so Cpk = 25 / (3 x 6) = 1.39. That meets a 1.33 target, but only just, and the 5 mV offset of the mean is worth explaining.
Characterization versus production test
| Characterization | Production test | |
|---|---|---|
| Purpose | Learn how the silicon behaves and set limits | Screen each unit against those limits |
| Parts tested | Sample, including corner lots | Every unit |
| Conditions | Many voltages, temperatures and frequencies, beyond spec | A few chosen conditions |
| Test time | Minutes to hours per part | Seconds per part |
| Output | Datasheet values, test limits, design feedback | Pass, fail and bin per unit |
Reliability qualification is a third, separate activity. It stresses parts over time, for example with high-temperature operating life tests, to show that they will keep meeting their specifications in the field.
Common mistakes
- Too few parts or only typical silicon. A handful of typical parts says little about the slow corner at hot temperature.
- Ignoring tester correlation. Bench and ATE results must agree before characterization limits are used in production.
- No guard band. Production limits set exactly at the measured edge leave nothing for tester accuracy, temperature error or ageing.
- Testing only inside the specification. Going beyond the specified range is how the real margin is found.
- Treating it as a one-off. Process, package and site changes all need a re-check.
FAQ
Is characterization testing done on every chip?
No. It is done on a sample of parts. Every chip goes through production test, using limits that characterization helped set.
What equipment is used?
Probe stations and parametric analysers for wafer-level device work, ATE for large-scale electrical tests, and bench instruments such as oscilloscopes, source measure units and signal analysers, all combined with thermal forcing or chambers.
What is a shmoo plot?
A grid of pass and fail results across two swept conditions, usually supply voltage and frequency, used to see the operating window of a part.
How long does characterization take?
It depends on the product. For a complex SoC it usually runs over several months, from first silicon through to production release.
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