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Showing posts with the label Kits

Kits

Questa SV/AFV: Verification Methodology Kits

mg -2:38 PM BBC 1

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ModelSim PE Student Edition - Free HDL Simulation

2:50 PM BBC 3

Unit delay simulation - an intermediate step in Gate level simulation!

3:01 PM BBC 3

Transport delay / Inertial Delay

5:13 PM BBC 3

Some good Puzzles / Interview questions

11:46 AM BBC 3

Digital "Greatest Common Divisor (GCD)" - Euclid’s algorithm

7:08 PM BBC 3

Interview Questions (Intel)

2:35 AM BBC 3

Pipelining Interview Question

6:51 PM BBC 3

Verilog Shift Register with Test Bench

5:35 PM BBC 3

Soft Macro Vs Hard macro?

5:50 PM BBC 3

RTL synthesis and other backend Interview Questions (with answers)

9:35 PM BBC 3

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