Zero delay simulation , Why and When

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Zero-delay simulation is a technique that is widely used in digital design verification, especially for gate-level netlist simulation. The goal of zero-delay simulation is to verify the basic functionality and liveness of the synthesized design without considering the timing delays of the gates and wires. 

Zero-delay simulation is a fast and efficient way to verify the basic functionality of the synthesized design, but it cannot guarantee its timing correctness and reliability. Therefore, it should be used as a preliminary step before performing more accurate and comprehensive timing simulation.This can be useful for several reasons:
  • Can run much faster than timing simulation, which requires SDF (Standard Delay Format) files to annotate the delays of each element in the netlist. This can save a lot of simulation time and resources, especially for large and complex designs.
  • Can be used to check the logical equivalence between the netlist and the RTL (Register Transfer Level) code, which is the original source code for synthesis. This can be done by using formal verification tools, such as Cadence Conformal LEC or Synopsys Formality, or by running the same testbench on both the netlist and the RTL and comparing the outputs. This can help to detect any synthesis errors or mismatches that may cause functional bugs or performance degradation.
  • Can also be used to verify the behavior of some special blocks or features that are not modeled by timing simulation, such as analog blocks (e.g., PLL, transceivers, memories), asynchronous resets, clock domain crossing, etc. These blocks may have different models or black boxes for zero-delay simulation and timing simulation, and they may have different effects on the rest of the design.
In summary, zero-delay simulation is not sufficient to ensure the correctness and robustness of the design. It cannot capture the effects of timing delays, such as setup and hold violations, glitches, metastability, etc., which may cause functional failures or data corruption. Therefore, zero-delay simulation should be complemented by timing simulation, which can verify the design under realistic timing conditions and constraints. Timing simulation can also validate the results of static timing analysis (STA), which is a tool that checks if the design meets the timing requirements without actually simulating it.

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