Acceleration And Emulation – Why HW/SW Integration Needs Both
Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play.…
Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play.…
Nokia's N8 is now official would see a launch during April. With a packed design that includes a 12 megapixel came…
Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called …
In response to the iPhone 4g post i ran yesterday i got quite a few comments and i want to highlight one of them specif…
" Google has purchased Agnilux , a secretive chip house made up of engineers who architected the heart of the iP…
A 100-year-old networking trick could boost transmissions over telephone infrastructure. Alcatel-Lucent has developed …
PCI Express-based MicroTCA platforms are generating more and more interest. This paper describes how small and cost-e…
With the dramatic increase in development costs for state-of-the-art process technologies, such as next-generation aut…
Since the introduction of the original USB standard in 1996, the USB interface has become one of the most successful c…
HP Home is the official HP website for personal computers, printing and imaging, servers and storage products for cons…
Virtualization technology has been used in high-end servers for quite some time. The evolution of virtualization has b…
This white paper introduces a new category of programmable logic devices, the Tabula ABAX family based on Spacetime a…
Organizations need to know how changing requirements in a complex system will affect development. An effective change …
With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed tes…
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is …
This application note describes FPGAs (field-programmable gate arrays) and how they can hold the key functions and th…
Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, an…
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integra…
The following is a list of conferences specific to the VLSI industry. It was earlier part of a widget on the sidebar bu…
Now you can post a job on this blog for as low as $15/Week or $30/Month ! This blog receives approx 25,000 page views …
Taking a floating-point representation of an algorithm into a fixed-point representation is an integral step on the pat…
Sometimes the delay through a component is dependent upon the values on signals. This is because different paths in the…
Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is des…
This application note from synopsys describes the advanced on-chip variation (OCV) solution in PrimeTime, including th…
A paper (PDF) to be presented later this month at the IEEE International Parallel and Distributed Processing Symposi…
This webcast highlights The SPIRIT Consortium's new IP-XACT 1.4 specification which expands the range of IP that c…
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-ac…
Splint is a tool for statically checking C programs for security vulnerabilities and coding mistakes. With minimal e…
Source Navigator for Verilog is full featured tool for editing and navigating through large projects with many Verilog…
Comit-TX extracts a self-checking Verilog testbench of any module inside a design that has a system level testbench.…
With thousands of Tapeouts, Conformal ASIC is the most widely-supported equivalency checking tool in the industry. It…
nECO is an integrated graphical netlist modification tool for the Verdi and Debussy debug systems. The Novas debug syst…
The Identify RTL Debugger lets FPGA designers and ASIC prototyping designers to functionally debug their hardware direc…
Synopsys, Inc. has introduced Design Compiler 2010, the latest RTL synthesis innovation within the Galaxy™ Implementati…
Because of shrinking feature sizes and the decreasing faithfulness of the manufacturing process to design features, pro…
Based on the competency level of the applicants we reserve the right to offer a free service or charge a minimum admini…
The semiconductor industry is struggling to maintain its momentum down the path of Moore’s Law, and it is becoming clea…
VN-Cover Emulator by TransEDA enables engineers to obtain coverage on their SoCs in a hardware-accelerated environment …
VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN…
The articles, publications and shared documents are included in this blog by the contributing authors as a mechanism t…
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
Cell phone radiation. Some consider it a heath-hazard of paramount importance. Others couldn't care less. Whichever…
The entire windshield is turned into a transparent display to highlighting landmarks, obstacles and road edges on the w…
ISuppli's final global revenue ranking for the top 25 semiconductor suppliers in 2009, in millions of U.S. dollars…
With increasing analog and mixed-signal content on systems-on-chip, design teams are looking for faster ways to run sys…
Electronics designs have become extremely complex and intricate, creating a need for software tools that support automa…
A communication device receives a clock up to X MHz. Write a verilog to verify that the clock meets this timing require…
Consider the Boolean function F = ( x1 + x3 + x4 )(x2 + x3 + x4 )(x1 + x2 +x4)(x1 +x3 +x4)( x1 +x2 + x3 ). Find an…
Packets dispatched can be of 3 network types: atm, ieee or Ethernet. The packets have a Boolean flag field which indica…