Coarse and Fine Grained FPGA Architectures Explained

Coarse-grained and fine-grained architectures differ in the size of the basic logic block in a programmable device. A fine-grained device uses many small, simple cells such as two-input gates or small multiplexers, while a coarse-grained device uses fewer, larger blocks built from look-up tables (LUTs) and flip-flops, or even word-wide ALUs. Larger blocks need fewer routing hops and are usually faster; smaller blocks waste less logic on small functions.

Key takeaways

"Grain" means the size and capability of the basic logic block.
A 4-input LUT is effectively a 16x1 ROM and can implement any function of four inputs.
Coarser blocks reduce the number of blocks and routing switches on a path, which usually improves speed.
Finer blocks give better utilization for small, irregular logic but need much more routing.
Modern FPGAs are heterogeneous: LUT-based logic plus very coarse blocks such as DSP slices and block RAM.

Coarse-grained and fine-grained defined

Coarse-grained architectures consist of fairly large logic blocks, often containing two or more look-up tables and two or more flip-flops. In a majority of these architectures, a four-input look-up table (think of it as a 16x1 ROM) implements the actual logic. The larger logic blocks usually correspond to improved performance.

Fine-grained circuits consist of a basic cell that is simple (OR, AND, and NOT).

Comparison table

Property	Fine-grained	Coarse-grained
Basic block	Simple gate, small mux or transistor pair	One or more LUTs plus flip-flops, or a word-wide ALU
Blocks per function	Many	Few
Routing needed	High; most area and delay is in interconnect	Lower; more logic stays inside a block
Speed	Lower for wide functions, many hops	Higher, fewer hops
Utilization on small functions	Good, little waste	Can waste part of a block
Typical examples	Early gate-array style and multiplexer-based FPGAs	LUT-based FPGAs, CGRAs with ALU arrays

Why a LUT is a 16x1 ROM

A 4-input LUT stores 16 configuration bits, one for every combination of its four inputs. The inputs act as an address and select one stored bit as the output. Loading a different 16-bit pattern changes the function, so one LUT can implement any of the 65,536 possible functions of four inputs.

The model below compiles in any Verilog simulator. For f = (a AND b) OR (c AND d), with the select bits ordered {d, c, b, a}, f is 1 at addresses 3, 7, 11, 12, 13, 14 and 15, giving the configuration value 16'hF888.

module lut4 #(parameter [15:0] INIT = 16'h0000) (
  input  wire [3:0] sel,   // {d, c, b, a}
  output wire       o
);
  assign o = INIT[sel];
endmodule

// f = (a & b) | (c & d)
module f_ab_or_cd (input wire a, b, c, d, output wire f);
  lut4 #(.INIT(16'hF888)) u_lut (.sel({d, c, b, a}), .o(f));
endmodule

Worked examples: counting blocks and levels

Function	2-input gates (fine)	4-input LUTs	6-input LUTs
(a AND b) OR (c AND d)	3 gates, 2 levels	1 LUT, 1 level	1 LUT, 1 level
8-input AND	7 gates, 3 levels	3 LUTs, 2 levels	2 LUTs, 2 levels
1-bit full adder (sum and carry)	5 gates (2 XOR, 2 AND, 1 OR)	2 LUTs, 1 level	2 LUTs, or 1 fracturable LUT

Every level of logic in a programmable device also means a trip through the routing fabric, which is often slower than the logic itself. Fewer levels is the main reason larger blocks perform better. Real FPGAs also add dedicated carry chains so adders do not use general routing at all.

Where CPLDs fit

CPLDs use a different kind of coarse block: the macrocell, fed by a wide programmable AND array that produces sum-of-products terms, with a flip-flop at the output. A few macrocells connected through one central switch matrix give short, predictable delays, which is why CPLDs suit wide decoding and state machines, for example the glue logic that connects processors to memory and I/O.

How the idea has changed since 2005

Note (2026): the 4-input LUT described in the original post was standard in FPGAs of that time. Since the mid-2000s, mainstream FPGAs have moved to 6-input LUTs or fracturable LUTs that can be split into two smaller functions, and they add very coarse hard blocks: DSP multiply-accumulate slices, block RAM, high-speed transceivers and, in some families, AI engines or processor cores. The term "coarse-grained reconfigurable array" (CGRA) is now used mainly for arrays of word-level processing elements, which sit between FPGAs and processors.

For a sense of how LUT counts relate to ASIC gate counts, see ASIC equivalent gates for Virtex, and for how coarse blocks are used in accelerators, see FPGA based customized acceleration.

Common interview follow-ups

Why not make LUTs much larger? LUT storage doubles with each extra input, and delay through the LUT grows, so beyond about six inputs the area cost outweighs the saving in routing.
What dominates delay in an FPGA? Usually routing, which is why reducing logic levels matters.
Is an ASIC standard cell library fine-grained? In this vocabulary, yes: cells are small gates, but there is no programmable routing penalty because wires are fixed at manufacture.

Frequently asked questions

Is an FPGA fine-grained or coarse-grained?

A LUT-based FPGA is usually described as coarse-grained compared with gate-level cells, though CGRA researchers call it fine-grained because it works on single bits. The context sets the scale.

What is a coarse-grained reconfigurable array?

A device built from word-wide processing elements such as ALUs and multipliers connected by a programmable network, aimed at data-parallel computing.

Why do larger logic blocks improve performance?

More logic is done inside each block, so a path passes through fewer programmable routing switches, which are a major source of delay.

How many functions can a 4-input LUT implement?

All of them: 2 to the power 16, or 65,536 functions.

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