FPGA & ASIC based design


The main diferrence between ASIC and FPGA based design is in the Back-end.
In FPGAs there is not much activities in back end.

FPGA flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> TRANSLATION -> MAPPING -> PLACE & ROUTE -> BITGEN GENERATION -> DOWNLOAD TO THE CHIP.

ASIC flow:
SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> SYNTHESIS -> EXTRACT RC VALUES -> DRC, LVS,etc., -> LIBRARY VENDOR SPECIFIC FILE FORMAT

{ 6 Reactions ... read them below or write one }

andy said on September 15, 2007 at 3:47 PM

Hi I would like to restate the ASIC flow mentioned above .

SPEC -> RTL -> FUNC. VERIF -> SYNTHESIS -> FORMAL VERIFICATION -> BACKEND ( floor plan , P&R , CTS ) -> FORMAL VERIFICATION -> POST LAYOUT STA -> LVS / DRC -> TAPEOUT

Murugavel said on October 19, 2007 at 1:55 PM

Thanks Andy. It is indeed more accurate.

vlsi.help said on February 28, 2008 at 11:56 AM

Thanks for info

Anonymous said on February 28, 2008 at 11:57 AM

Thanks for info .............

OutputLogic said on October 24, 2009 at 12:02 PM

Correction to the FPGA flow:

SPECIFICATION -> RTL DESIGN -> FUNCTIONAL SIMULATION -> Constraints and Floorplan -> SYNTHESIS -> TRANSLATION -> MAPPING -> PLACE & ROUTE -> BITGEN GENERATION -> DOWNLOAD TO THE CHIP.

mg said on November 25, 2009 at 6:59 PM

Bring it on!

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