- A configuration declaration is needed for each architecture in the design
- Design-internal references must use library work
- Use selected names in binding indications and ’use’ clauses only
- Configuration must be in a separated file except the latest level of hierarchy
- All primary unit names must be unique in the project library
- Identifier casing should be uniform in all VHDL code
- Length of entity names should not exceed 32 characters
- An instance name must not contain the substring ’pfiller’
- Use unresolved data types if possible
- Hard/firm macros: Data types at ports: std_(u)logic(_vector)
- Generics must have type integer for synthesis
- Avoid feedthroughs
- Strength stripping should be performed on chip level
- Do not assign the value 'X'
- Asynchronous reset is mandatory for sequential processes
- Do not use internal three-state busses
- Use the predefined templates for component instantiation
- Refer to one edge of clock, only
- Do not use combinational feedback loops
- Global signals may be used for testing purposes only
- Use relative path names for files accessed through text-IO
- Binary file-IO may not be used
- In association lists of generic maps and port maps use named association
- VHDL-93 keywords should not be used
- Verilog keywords should not be used
- SDF keywords should not be used
- IKOS keywords should not be used
- Allowable replacement characters are forbidden
- Tool specific types may not be used
- Configuration declarations must have the configuration name and the entity name in one line for vimport
- Never redefine standard operators, subprograms, attributes, and packages
- Language for modeling is VHDL-87
- Comparison of arrays must be based on arrays of the same width
- Bussed arithmetic objects use "downto" as their index orientation
- Store package header and body into same file
- Default values for ports, signals, and variables may not be used
- Data types must be synthesizable
- Array ranges must be of type integer
- Integer type objects must be constrained with respect to to their range
- Use standard templates for clocked processes
- Generics must have type integer
- Order of generics in entity, component and instance must be the same
- Place port and generic maps at the component instantiation
- Instantiated component and entity name must be equal, incl. casing
- The sensitivity list for combinational processes must be complete
- Write variables before read in combinational logic
- Bit-wise association of arrays in port maps is not possible in presence of generics
- Embedding scripts as meta comments is not acceptable
- Use only standard meta comments
- Code for synthesis must match the synthesis subset
- Do not use disconnect, register, and bus
- Do not use port modes buffer and linkage
- Do not use configuration specification (“hard binding”)
- Do not use blocks
- Avoid identifier hiding caused by loop index
- Recursive use of subprograms is forbidden
- Do not use guarded signals, guarded assignments, and guarded expressions
- Trailing comments are only allowed for declarative lists
HDL Coding Guidelines - Part 4
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January 20, 2008
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To Avoid common Errors
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