NOTES:
1.
2. The capacitance of an individual gate (e.g. AND, OR) is 1.
3. The capacitance of a flip flop is 2.
4. The circuit uses a valid-bit protocol to distinguish between valid and invalid data. The valid bit arrives in the same clock cycle as the valid data.
5. The environment sends valid data once every 5 clock cycles (e.g. one clock cycle with valid data, followed by 4 clock cycles of invalid data).
6. Your power reduction scheme shall not:
change the clock speed or any characteristics of the implementation technology (e.g. supply orthreshold voltage).
add or delete any signals between the circuit and the environment.
change the functional behaviour of the circuit for valid data.
7. Your power reduction scheme may increase the latency of the pipeline
Describe/illustrate your power reduction scheme. Calculate how much less power (as a percentage) the new circuit (i.e. with your scheme) consumes compared to the original circuit (i.e. without the power reduction scheme).
whats the answer? register the valid and use it to gate the clock to the blocks?
ReplyDeleteI am thinking one can use a Mux before 'data' to choose from 'data' input and '0' input. 'valid' bit will be the select input to this mux. Since the data is invalid for 5 clock cycles, the 'valid' bit would be zero and hence would select '0' input of the Mux. Even though the data may be changing for the next 4 cycles the '0' input is selected instead of 'data' For these 4 cycles there is no switching activity. Thus power is reduced.
ReplyDelete